Altera UG-01080 Guía de usuario Pagina 426

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16–48 Chapter 16: Transceiver Reconfiguration Controller IP Core
Merging TX PLLs In Multiple Transceiver PHY Instances
Altera Transceiver PHY IP Core November 2012 Altera Corporation
User Guide
Merging TX PLLs In Multiple Transceiver PHY Instances
The Quartus II Fitter can merge the TX PLLs for multiple transceiver PHY IP cores
under the following conditions:
The PLLs connect to the same reset pin.
The PLLs connect to the same reference clock.
The PLLs connect to the same Transceiver Reconfiguration Controller.
Figure 16–13 illustrates a design where the CMU PLL in channel 1 provides the clock
to three Custom PHY channels and two 10GBASE-R PHY channels.
Figure 16–13. PLL Shared by Multiple Transceiver PHY IP Cores in a Single Transceiver Bank
Transceiver Bank
to Embedded
Processor
Reconfig to
and from
Transceiver
Stratix V GX, GS, or GT Device
S M
3 Transceiver
Channels
Custom
10 GBASE-R
10 GBASE-R
Transceiver
Reconfiguration
Controller
3 Transceiver
Channels
Custom
Custom
CMU PLL
S
S
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