Altera UG-01080 Guía de usuario

101 Innovation DriveSan Jose, CA 95134www.altera.com UG-01080-1.8User GuideAltera Transceiver PHY IP CoreDocument last updated for Altera Complete Des

x ContentsContentsAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideOffset Cancellation . . . . . . . . . . . . . . . . . . .

Chapter 5: 1G/10 Gbps Ethernet PHY IP Core 5–12Register Interface and Register DescriptionsNovember 2012 Altera CorporationAltera Transceiver PHY IP C

Chapter 5: 1G/10 Gbps Ethernet PHY IP Core 5–13Register Interface and Register DescriptionsNovember 2012 Altera CorporationAltera Transceiver PHY IP C

Chapter 5: 1G/10 Gbps Ethernet PHY IP Core 5–14Register Interface and Register DescriptionsNovember 2012 Altera CorporationAltera Transceiver PHY IP C

Chapter 5: 1G/10 Gbps Ethernet PHY IP Core 5–15Register Interface and Register DescriptionsNovember 2012 Altera CorporationAltera Transceiver PHY IP C

Chapter 5: 1G/10 Gbps Ethernet PHY IP Core 5–16Register Interface and Register DescriptionsNovember 2012 Altera CorporationAltera Transceiver PHY IP C

Chapter 5: 1G/10 Gbps Ethernet PHY IP Core 5–17Dynamic Reconfiguration from 1G to 10GbENovember 2012 Altera CorporationAltera Transceiver PHY IP CoreU

Chapter 5: 1G/10 Gbps Ethernet PHY IP Core 5–18Dynamic Reconfiguration from 1G to 10GbENovember 2012 Altera CorporationAltera Transceiver PHY IP CoreU

Chapter 5: 1G/10 Gbps Ethernet PHY IP Core 5–19Creating a 1G/10GbE DesignNovember 2012 Altera CorporationAltera Transceiver PHY IP CoreUser GuideState

Chapter 5: 1G/10 Gbps Ethernet PHY IP Core 5–20Editing a MIF FileNovember 2012 Altera CorporationAltera Transceiver PHY IP CoreUser Guide8. Generate a

Chapter 5: 1G/10 Gbps Ethernet PHY IP Core 5–21Design ExamplesNovember 2012 Altera CorporationAltera Transceiver PHY IP CoreUser GuideExample 5–1 illu

ContentsContents xiNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideChapter 19. Migrating from Stratix IV to Stratix V Devices

Chapter 5: 1G/10 Gbps Ethernet PHY IP Core 5–22Dynamic ReconfigurationNovember 2012 Altera CorporationAltera Transceiver PHY IP CoreUser GuideDynamic

Chapter 5: 1G/10 Gbps Ethernet PHY IP Core 5–23SimulationNovember 2012 Altera CorporationAltera Transceiver PHY IP CoreUser GuideSimulationThe 1G/10Gb

5–24 Chapter 5: 1G/10 Gbps Ethernet PHY IP CoreAcronymsAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guide

November 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide6. XAUI PHY IP CoreThe Altera XAUI PHY IP Core implements the IEEE 802.3 Clau

6–2 Chapter 6: XAUI PHY IP CoreRelease InformationAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideRelease InformationTable 6–

Chapter 6: XAUI PHY IP Core 6–3Performance and Resource Utilization for Stratix IV DevicesNovember 2012 Altera Corporation Altera Transceiver PHY IP C

6–4 Chapter 6: XAUI PHY IP CoreGeneral ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideGeneral ParametersTable 6–4

Chapter 6: XAUI PHY IP Core 6–5Analog ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideExample 6–1 shows how to remo

6–6 Chapter 6: XAUI PHY IP CoreAnalog Parameters for Arria II GX, Cyclone IV GX, HardCopy IV and Stratix IV DevicesAltera Transceiver PHY IP Core Nove

Chapter 6: XAUI PHY IP Core 6–7Advanced Options ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideAdvanced Options Pa

xii ContentsContentsAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guide

6–8 Chapter 6: XAUI PHY IP CoreConfigurationsAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideConfigurationsFigure 6–2 illustr

Chapter 6: XAUI PHY IP Core 6–9PortsNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide1 The block diagram shown in the GUI labe

6–10 Chapter 6: XAUI PHY IP CoreData InterfacesAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideFigure 6–4 illustrates the top

Chapter 6: XAUI PHY IP Core 6–11Data InterfacesNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideFor the DDR XAUI variant, the

6–12 Chapter 6: XAUI PHY IP CoreData InterfacesAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideSDR XGMII TX InterfaceTable 6–

Chapter 6: XAUI PHY IP Core 6–13Clocks, Reset, and Powerdown InterfacesNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideClocks

6–14 Chapter 6: XAUI PHY IP CorePMA Channel Controller InterfaceAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuidePMA Channel C

Chapter 6: XAUI PHY IP Core 6–15Optional PMA Control and Status InterfaceNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideTabl

6–16 Chapter 6: XAUI PHY IP CoreOptional PMA Control and Status InterfaceAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guiderx_d

Chapter 6: XAUI PHY IP Core 6–17Register Interface and Register DescriptionsNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideR

November 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide1. IntroductionThe Altera® Transceiver PHY IP Core User Guide describes the f

6–18 Chapter 6: XAUI PHY IP CoreRegister Interface and Register DescriptionsAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideR

Chapter 6: XAUI PHY IP Core 6–19Register Interface and Register DescriptionsNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide0

6–20 Chapter 6: XAUI PHY IP CoreRegister Interface and Register DescriptionsAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guide0

Chapter 6: XAUI PHY IP Core 6–21Dynamic Reconfiguration for Arria II GX, Cyclone IV GX, HardCopy IV GX, and Stratix IV GXNovember 2012 Altera Corporat

6–22 Chapter 6: XAUI PHY IP CoreDynamic Reconfiguration for Arria V, Cyclone V and Stratix V DevicesAltera Transceiver PHY IP Core November 2012 Alter

Chapter 6: XAUI PHY IP Core 6–23Simulation Files and Example TestbenchNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideAssignm

6–24 Chapter 6: XAUI PHY IP CoreSimulation Files and Example TestbenchAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guide

November 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide7. Interlaken PHY IP CoreInterlaken is a high speed serial communication prot

7–2 Chapter 7: Interlaken PHY IP CoreDevice Family SupportAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guide Lane-based CRC32

Chapter 7: Interlaken PHY IP Core 7–3General ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide5. Click Finish to gen

1–2 Chapter 1: IntroductionAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guide Native Transceiver PHYs—These PHYs provide compl

7–4 Chapter 7: Interlaken PHY IP CoreOptional Port ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideOptional Port Pa

Chapter 7: Interlaken PHY IP Core 7–5InterfacesNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideInterfacesFigure 7–2 illustrat

7–6 Chapter 7: Interlaken PHY IP CoreAvalon-ST TX InterfaceAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideAvalon-ST TX Inter

Chapter 7: Interlaken PHY IP Core 7–7Avalon-ST TX InterfaceNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guidetx_readyOutputWhen

7–8 Chapter 7: Interlaken PHY IP CoreAvalon-ST RX InterfaceAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideAvalon-ST RX Inter

Chapter 7: Interlaken PHY IP Core 7–9Avalon-ST RX InterfaceNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guiderx_parallel_data&l

7–10 Chapter 7: Interlaken PHY IP CoreAvalon-ST RX InterfaceAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guiderx_parallel_data&

Chapter 7: Interlaken PHY IP Core 7–11TX and RX Serial InterfaceNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideTX and RX Ser

7–12 Chapter 7: Interlaken PHY IP CoreOptional Clocks for DeskewAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideOptional Cloc

Chapter 7: Interlaken PHY IP Core 7–13Register Interface and Register DescriptionsNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser

Chapter 1: Introduction 1–3November 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideFor detailed information about these IP cores, ref

7–14 Chapter 7: Interlaken PHY IP CoreRegister Interface and Register DescriptionsAltera Transceiver PHY IP Core November 2012 Altera CorporationUser

Chapter 7: Interlaken PHY IP Core 7–15Why Transceiver Dynamic ReconfigurationNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide

7–16 Chapter 7: Interlaken PHY IP CoreDynamic Transceiver Reconfiguration InterfaceAltera Transceiver PHY IP Core November 2012 Altera CorporationUser

November 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide8. PHY IP Core for PCI Express (PIPE)The Altera PHY IP Core for PCI Express

8–2 Chapter 8: PHY IP Core for PCI Express (PIPE)Device Family SupportAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guidef For m

Chapter 8: PHY IP Core for PCI Express (PIPE) 8–3Parameterizing the PHY IP Core for PCI Express (PIPE)November 2012 Altera Corporation Altera Transcei

8–4 Chapter 8: PHY IP Core for PCI Express (PIPE)General Options ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideFP

Chapter 8: PHY IP Core for PCI Express (PIPE) 8–5InterfacesNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideInterfacesThis sec

8–6 Chapter 8: PHY IP Core for PCI Express (PIPE)PIPE Input Data from the PHY MACAltera Transceiver PHY IP Core November 2012 Altera CorporationUser G

Chapter 8: PHY IP Core for PCI Express (PIPE) 8–7PIPE Input Data from the PHY MACNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser G

1–4 Chapter 1: IntroductionAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideTransceiver Reconfiguration ControllerAltera Trans

8–8 Chapter 8: PHY IP Core for PCI Express (PIPE)PIPE Input Data from the PHY MACAltera Transceiver PHY IP Core November 2012 Altera CorporationUser G

Chapter 8: PHY IP Core for PCI Express (PIPE) 8–9PIPE Output Data to the PHY MACNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Gu

8–10 Chapter 8: PHY IP Core for PCI Express (PIPE)ClocksAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideFigure 8–4 illustrate

Chapter 8: PHY IP Core for PCI Express (PIPE) 8–11Optional Status InterfaceNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideTa

8–12 Chapter 8: PHY IP Core for PCI Express (PIPE)Serial Data InterfaceAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideSerial

Chapter 8: PHY IP Core for PCI Express (PIPE) 8–13Register Interface and Register DescriptionsNovember 2012 Altera Corporation Altera Transceiver PHY

8–14 Chapter 8: PHY IP Core for PCI Express (PIPE)Register Interface and Register DescriptionsAltera Transceiver PHY IP Core November 2012 Altera Corp

Chapter 8: PHY IP Core for PCI Express (PIPE) 8–15Register Interface and Register DescriptionsNovember 2012 Altera Corporation Altera Transceiver PHY

8–16 Chapter 8: PHY IP Core for PCI Express (PIPE)Register Interface and Register DescriptionsAltera Transceiver PHY IP Core November 2012 Altera Corp

Chapter 8: PHY IP Core for PCI Express (PIPE) 8–17Link Equalization for Gen3 Data RateNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreU

Chapter 1: Introduction 1–5Running a Simulation TestbenchNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideRunning a Simulation

8–18 Chapter 8: PHY IP Core for PCI Express (PIPE)Link Equalization for Gen3 Data RateAltera Transceiver PHY IP Core November 2012 Altera CorporationU

Chapter 8: PHY IP Core for PCI Express (PIPE) 8–19Link Equalization for Gen3 Data RateNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreU

8–20 Chapter 8: PHY IP Core for PCI Express (PIPE)Enabling Dynamic PMA Tuning for PCIe Gen3Altera Transceiver PHY IP Core November 2012 Altera Corpora

Chapter 8: PHY IP Core for PCI Express (PIPE) 8–21Simulation Files and Example TestbenchNovember 2012 Altera Corporation Altera Transceiver PHY IP Cor

8–22 Chapter 8: PHY IP Core for PCI Express (PIPE)Simulation Files and Example TestbenchAltera Transceiver PHY IP Core November 2012 Altera Corporatio

November 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide9. Custom PHY IP CoreThe Altera Custom PHY IP Core is a generic PHY that you

9–2 Chapter 9: Custom PHY IP CoreDevice Family SupportAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideFigure 9–1 illustrates

Chapter 9: Custom PHY IP Core 9–3Parameterizing the Custom PHYNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideParameterizing

9–4 Chapter 9: Custom PHY IP CoreGeneral Options ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideBonding mode×1×Nfb

Chapter 9: Custom PHY IP Core 9–5General Options ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuidePLL typeCMUATXThe

1–6 Chapter 1: IntroductionUnsupported FeaturesAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideThe Verilog and VHDL transceiv

9–6 Chapter 9: Custom PHY IP CoreGeneral Options ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideThe CDR can be put

Chapter 9: Custom PHY IP Core 9–7Word Alignment ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideWord Alignment Para

9–8 Chapter 9: Custom PHY IP CoreRate Match FIFO ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideTable 9–5 provides

Chapter 9: Custom PHY IP Core 9–98B/10B Encoder and Decoder ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide8B/10B

9–10 Chapter 9: Custom PHY IP CoreByte Order ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guide1 You cannot enable Ra

Chapter 9: Custom PHY IP Core 9–11Byte Order ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideByte ordering patternD

9–12 Chapter 9: Custom PHY IP CorePLL Reconfiguration ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuidePLL Reconfigu

Chapter 9: Custom PHY IP Core 9–13Analog ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideAnalog ParametersClick on

9–14 Chapter 9: Custom PHY IP CoreInterfacesAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideInterfacesFigure 9–2 illustrates

Chapter 9: Custom PHY IP Core 9–15Data InterfacesNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide <p>—The number of PL

November 2012 Altera Corporation Altera Transceiver PHY IP Core2. Getting StartedThis chapter provides a general overview of the Altera IP core design

9–16 Chapter 9: Custom PHY IP CoreData InterfacesAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideTable 9–12 describes the sig

Chapter 9: Custom PHY IP Core 9–17Clock InterfaceNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideClock InterfaceTable 9–14 de

9–18 Chapter 9: Custom PHY IP CoreOptional Reset Control and Status InterfaceAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guide

Chapter 9: Custom PHY IP Core 9–19Register Interface and Register DescriptionsNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guid

9–20 Chapter 9: Custom PHY IP CoreRegister Interface and Register DescriptionsAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guid

Chapter 9: Custom PHY IP Core 9–21Register Interface and Register DescriptionsNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guid

9–22 Chapter 9: Custom PHY IP CoreRegister Interface and Register DescriptionsAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guid

Chapter 9: Custom PHY IP Core 9–23Dynamic ReconfigurationNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideDynamic Reconfigurat

9–24 Chapter 9: Custom PHY IP CoreSimulation Files and Example TestbenchAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideAssig

November 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide10. Low Latency PHY IP CoreThe Altera Low Latency PHY IP Core receives and tr

© 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logosare trademar

2–2 Chapter 2: Getting StartedMegaWizard Plug-In Manager FlowAltera Transceiver PHY IP Core November 2012 Altera Corporation MegaWizard™ Plug-In Mana

10–2 Chapter 10: Low Latency PHY IP CorePerformance and Resource Utilization - Need UpdateAltera Transceiver PHY IP Core November 2012 Altera Corporat

Chapter 10: Low Latency PHY IP Core 10–3General Options ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide1. For Whic

10–4 Chapter 10: Low Latency PHY IP CoreGeneral Options ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideBonding mod

Chapter 10: Low Latency PHY IP Core 10–5Additional Options ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideTable 10

10–6 Chapter 10: Low Latency PHY IP CoreAdditional Options ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideTable 10

Chapter 10: Low Latency PHY IP Core 10–7PLL Reconfiguration ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuidePLL Rec

10–8 Chapter 10: Low Latency PHY IP CorePLL Reconfiguration ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideCDR PLL

Chapter 10: Low Latency PHY IP Core 10–9Analog ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideAnalog ParametersFor

10–10 Chapter 10: Low Latency PHY IP CoreData InterfacesAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideData InterfacesTable

Chapter 10: Low Latency PHY IP Core 10–11Optional Status InterfaceNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideOptional St

Chapter 2: Getting Started 2–3MegaWizard Plug-In Manager FlowNovember 2012 Altera Corporation Altera Transceiver PHY IP Core2. In the Quartus II softw

10–12 Chapter 10: Low Latency PHY IP CoreOptional Reset Control and Status InterfaceAltera Transceiver PHY IP Core November 2012 Altera CorporationUse

Chapter 10: Low Latency PHY IP Core 10–13Register Interface and Register DescriptionsNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUs

10–14 Chapter 10: Low Latency PHY IP CoreDynamic ReconfigurationAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideDynamic Recon

Chapter 10: Low Latency PHY IP Core 10–15Simulation Files and Example TestbenchNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Gui

10–16 Chapter 10: Low Latency PHY IP CoreSimulation Files and Example TestbenchAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Gui

November 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide11. Deterministic Latency PHY IP CoreThe Altera Deterministic Latency PHY IP

11–2 Chapter 11: Deterministic Latency PHY IP CoreAuto-NegotiationAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideThe data th

Chapter 11: Deterministic Latency PHY IP Core 11–3Achieving Deterministic LatencyNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser G

11–4 Chapter 11: Deterministic Latency PHY IP CoreAchieving Deterministic LatencyAltera Transceiver PHY IP Core November 2012 Altera CorporationUser G

Chapter 11: Deterministic Latency PHY IP Core 11–5Delay Estimation LogicNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideDelay

2–4 Chapter 2: Getting StartedMegaWizard Plug-In Manager FlowAltera Transceiver PHY IP Core November 2012 Altera Corporation1 The Finish button may be

11–6 Chapter 11: Deterministic Latency PHY IP CoreDelay Estimation LogicAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideDelay

Chapter 11: Deterministic Latency PHY IP Core 11–7Device Family SupportNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideDevice

11–8 Chapter 11: Deterministic Latency PHY IP CoreGeneral Options ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideG

Chapter 11: Deterministic Latency PHY IP Core 11–9General Options ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideT

11–10 Chapter 11: Deterministic Latency PHY IP CoreAdditional Options ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Gu

Chapter 11: Deterministic Latency PHY IP Core 11–11PLL Reconfiguration ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser G

11–12 Chapter 11: Deterministic Latency PHY IP CoreAnalog ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideAnalog Pa

Chapter 11: Deterministic Latency PHY IP Core 11–13InterfacesNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideInterfacesFigure

11–14 Chapter 11: Deterministic Latency PHY IP CoreData InterfacesAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideData Interf

Chapter 11: Deterministic Latency PHY IP Core 11–15Data InterfacesNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideTable 11–12

November 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide3. 10GBASE-R PHY IP CoreThe Altera 10GBASE-R PHY IP Core implements the funct

11–16 Chapter 11: Deterministic Latency PHY IP CoreClock InterfaceAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideTable 11–14

Chapter 11: Deterministic Latency PHY IP Core 11–17Optional Reset Control and Status InterfacesNovember 2012 Altera Corporation Altera Transceiver PHY

11–18 Chapter 11: Deterministic Latency PHY IP CoreRegister Interface and Register DescriptionsAltera Transceiver PHY IP Core November 2012 Altera Cor

Chapter 11: Deterministic Latency PHY IP Core 11–19Register Interface and Register DescriptionsNovember 2012 Altera Corporation Altera Transceiver PHY

11–20 Chapter 11: Deterministic Latency PHY IP CoreRegister Interface and Register DescriptionsAltera Transceiver PHY IP Core November 2012 Altera Cor

Chapter 11: Deterministic Latency PHY IP Core 11–21Dynamic ReconfigurationNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideDyn

11–22 Chapter 11: Deterministic Latency PHY IP CoreChannel Placement and UtilizationAltera Transceiver PHY IP Core November 2012 Altera CorporationUse

Chapter 11: Deterministic Latency PHY IP Core 11–23Simulation Files and Example TestbenchNovember 2012 Altera Corporation Altera Transceiver PHY IP Co

11–24 Chapter 11: Deterministic Latency PHY IP CoreSimulation Files and Example TestbenchAltera Transceiver PHY IP Core November 2012 Altera Corporati

November 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide12. Stratix V Transceiver Native PHY IPCoreThe Stratix V Transceiver Native P

3–2 Chapter 3: 10GBASE-R PHY IP CoreAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guide1 This configuration does not require tha

12–2 Chapter 12: Stratix V Transceiver Native PHY IP CoreDevice Family SupportAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guid

Chapter 12: Stratix V Transceiver Native PHY IP Core 12–3Parameter PresetsNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuidePar

12–4 Chapter 12: Stratix V Transceiver Native PHY IP CoreGeneral ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideGe

Chapter 12: Stratix V Transceiver Native PHY IP Core 12–5PMA ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuidePMA Pa

12–6 Chapter 12: Stratix V Transceiver Native PHY IP CorePMA ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideTX PMA

Chapter 12: Stratix V Transceiver Native PHY IP Core 12–7PMA ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideTX PLL

12–8 Chapter 12: Stratix V Transceiver Native PHY IP CorePMA ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideRX CDR

Chapter 12: Stratix V Transceiver Native PHY IP Core 12–9PMA ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideTable

12–10 Chapter 12: Stratix V Transceiver Native PHY IP CorePMA ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideTable

Chapter 12: Stratix V Transceiver Native PHY IP Core 12–11Standard PCS ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser G

Chapter 3: 10GBASE-R PHY IP Core 3–3November 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideFigure 3–3 illustrates the 10GBASE-R PHY

12–12 Chapter 12: Stratix V Transceiver Native PHY IP CoreStandard PCS ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser G

Chapter 12: Stratix V Transceiver Native PHY IP Core 12–13Standard PCS ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser G

12–14 Chapter 12: Stratix V Transceiver Native PHY IP CoreStandard PCS ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser G

Chapter 12: Stratix V Transceiver Native PHY IP Core 12–15Standard PCS ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser G

12–16 Chapter 12: Stratix V Transceiver Native PHY IP CoreStandard PCS ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser G

Chapter 12: Stratix V Transceiver Native PHY IP Core 12–17Standard PCS ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser G

12–18 Chapter 12: Stratix V Transceiver Native PHY IP CoreStandard PCS ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser G

Chapter 12: Stratix V Transceiver Native PHY IP Core 12–1910G PCS ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide1

12–20 Chapter 12: Stratix V Transceiver Native PHY IP Core10G PCS ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideT

Chapter 12: Stratix V Transceiver Native PHY IP Core 12–2110G PCS ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guidef

3–4 Chapter 3: 10GBASE-R PHY IP CoreAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideFigure 3–5 illustrates the 10GBASE-R PHY

12–22 Chapter 12: Stratix V Transceiver Native PHY IP Core10G PCS ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guide1

Chapter 12: Stratix V Transceiver Native PHY IP Core 12–2310G PCS ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideE

12–24 Chapter 12: Stratix V Transceiver Native PHY IP Core10G PCS ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideI

Chapter 12: Stratix V Transceiver Native PHY IP Core 12–2510G PCS ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideI

12–26 Chapter 12: Stratix V Transceiver Native PHY IP Core10G PCS ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideE

Chapter 12: Stratix V Transceiver Native PHY IP Core 12–2710G PCS ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideI

12–28 Chapter 12: Stratix V Transceiver Native PHY IP Core10G PCS ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guide6

Chapter 12: Stratix V Transceiver Native PHY IP Core 12–2910G PCS ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideI

12–30 Chapter 12: Stratix V Transceiver Native PHY IP Core10G PCS ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideG

Chapter 12: Stratix V Transceiver Native PHY IP Core 12–31InterfacesNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideInterface

Chapter 3: 10GBASE-R PHY IP Core 3–5Release InformationNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideRelease InformationTab

12–32 Chapter 12: Stratix V Transceiver Native PHY IP CoreCommon Interface PortsAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Gu

Chapter 12: Stratix V Transceiver Native PHY IP Core 12–33Common Interface PortsNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Gu

12–34 Chapter 12: Stratix V Transceiver Native PHY IP CoreCommon Interface PortsAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Gu

Chapter 12: Stratix V Transceiver Native PHY IP Core 12–35Standard PCS Interface PortsNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreU

12–36 Chapter 12: Stratix V Transceiver Native PHY IP CoreStandard PCS Interface PortsAltera Transceiver PHY IP Core November 2012 Altera CorporationU

Chapter 12: Stratix V Transceiver Native PHY IP Core 12–37Standard PCS Interface PortsNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreU

12–38 Chapter 12: Stratix V Transceiver Native PHY IP Core10G PCS InterfaceAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guide10

Chapter 12: Stratix V Transceiver Native PHY IP Core 12–3910G PCS InterfaceNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideTa

12–40 Chapter 12: Stratix V Transceiver Native PHY IP Core10G PCS InterfaceAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guidetx

Chapter 12: Stratix V Transceiver Native PHY IP Core 12–4110G PCS InterfaceNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideRX

3–6 Chapter 3: 10GBASE-R PHY IP CorePerformance and Resource Utilization for Stratix IV DevicesAltera Transceiver PHY IP Core November 2012 Altera Cor

12–42 Chapter 12: Stratix V Transceiver Native PHY IP Core10G PCS InterfaceAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guiderx

Chapter 12: Stratix V Transceiver Native PHY IP Core 12–4310G PCS InterfaceNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guiderx

12–44 Chapter 12: Stratix V Transceiver Native PHY IP Core10G PCS InterfaceAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guidetx

Chapter 12: Stratix V Transceiver Native PHY IP Core 12–4510G PCS InterfaceNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guiderx

12–46 Chapter 12: Stratix V Transceiver Native PHY IP CoreSDC Timing ConstraintsAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Gu

Chapter 12: Stratix V Transceiver Native PHY IP Core 12–47Dynamic ReconfigurationNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser G

12–48 Chapter 12: Stratix V Transceiver Native PHY IP CoreSimulation SupportAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideA

November 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide13. Arria V Transceiver Native PHY IPCoreThe Arria V Transceiver Native PHY I

13–2 Chapter 13: Arria V Transceiver Native PHY IP CoreDevice Family SupportAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideI

Chapter 13: Arria V Transceiver Native PHY IP Core 13–3General ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideGene

Chapter 3: 10GBASE-R PHY IP Core 3–7Parameterizing the 10GBASE-R PHYNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideParameter

13–4 Chapter 13: Arria V Transceiver Native PHY IP CorePMA ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuidePMA Para

Chapter 13: Arria V Transceiver Native PHY IP Core 13–5PMA ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideTX PLL&l

13–6 Chapter 13: Arria V Transceiver Native PHY IP CorePMA ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideRX PMA P

Chapter 13: Arria V Transceiver Native PHY IP Core 13–7PMA ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideTable 13

13–8 Chapter 13: Arria V Transceiver Native PHY IP CoreStandard PCS ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guid

Chapter 13: Arria V Transceiver Native PHY IP Core 13–9Standard PCS ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guid

13–10 Chapter 13: Arria V Transceiver Native PHY IP CoreStandard PCS ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Gui

Chapter 13: Arria V Transceiver Native PHY IP Core 13–11Standard PCS ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Gui

13–12 Chapter 13: Arria V Transceiver Native PHY IP CoreStandard PCS ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Gui

Chapter 13: Arria V Transceiver Native PHY IP Core 13–13Standard PCS ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Gui

November 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideContentsChapter 1. IntroductionPCS . . . . . . . . . . . . . . . . . . . . .

3–8 Chapter 3: 10GBASE-R PHY IP CoreGeneral Option ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideExample 3–1 show

13–14 Chapter 13: Arria V Transceiver Native PHY IP CoreStandard PCS ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Gui

Chapter 13: Arria V Transceiver Native PHY IP Core 13–15InterfacesNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideInterfacesT

13–16 Chapter 13: Arria V Transceiver Native PHY IP CoreCommon Interface PortsAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guid

Chapter 13: Arria V Transceiver Native PHY IP Core 13–17Common Interface PortsNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guid

13–18 Chapter 13: Arria V Transceiver Native PHY IP CoreStandard PCS Interface PortsAltera Transceiver PHY IP Core November 2012 Altera CorporationUse

Chapter 13: Arria V Transceiver Native PHY IP Core 13–19Standard PCS Interface PortsNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUse

13–20 Chapter 13: Arria V Transceiver Native PHY IP CoreSDC Timing ConstraintsAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guid

Chapter 13: Arria V Transceiver Native PHY IP Core 13–21SDC Timing ConstraintsNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guid

13–22 Chapter 13: Arria V Transceiver Native PHY IP CoreDynamic ReconfigurationAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Gui

November 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide14. Arria V GZ Transceiver Native PHY IPCoreThe Arria V GZTransceiver Native

Chapter 3: 10GBASE-R PHY IP Core 3–9Analog ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideAnalog ParametersClick o

14–2 Chapter 14: Arria V GZ Transceiver Native PHY IP CoreDevice Family SupportAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Gui

Chapter 14: Arria V GZ Transceiver Native PHY IP Core 14–3Performance and Resource UtilizationNovember 2012 Altera Corporation Altera Transceiver PHY

14–4 Chapter 14: Arria V GZ Transceiver Native PHY IP CoreParameterizing the Arria V GZ Native PHYAltera Transceiver PHY IP Core November 2012 Altera

Chapter 14: Arria V GZ Transceiver Native PHY IP Core 14–5PMA ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuidePMA P

14–6 Chapter 14: Arria V GZ Transceiver Native PHY IP CorePMA ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideTX PM

Chapter 14: Arria V GZ Transceiver Native PHY IP Core 14–7PMA ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideTX PL

14–8 Chapter 14: Arria V GZ Transceiver Native PHY IP CorePMA ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideRX PM

Chapter 14: Arria V GZ Transceiver Native PHY IP Core 14–9PMA ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideTable

14–10 Chapter 14: Arria V GZ Transceiver Native PHY IP CorePMA ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideTabl

Chapter 14: Arria V GZ Transceiver Native PHY IP Core 14–11Standard PCS ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser

3–10 Chapter 3: 10GBASE-R PHY IP CoreInterfacesAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guide InterfacesFigure 3–6 illustra

14–12 Chapter 14: Arria V GZ Transceiver Native PHY IP CoreStandard PCS ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser

Chapter 14: Arria V GZ Transceiver Native PHY IP Core 14–13Standard PCS ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser

14–14 Chapter 14: Arria V GZ Transceiver Native PHY IP CoreStandard PCS ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser

Chapter 14: Arria V GZ Transceiver Native PHY IP Core 14–15Standard PCS ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser

14–16 Chapter 14: Arria V GZ Transceiver Native PHY IP CoreStandard PCS ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser

Chapter 14: Arria V GZ Transceiver Native PHY IP Core 14–17Standard PCS ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser

14–18 Chapter 14: Arria V GZ Transceiver Native PHY IP CoreStandard PCS ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser

Chapter 14: Arria V GZ Transceiver Native PHY IP Core 14–1910G PCS ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide

14–20 Chapter 14: Arria V GZ Transceiver Native PHY IP Core10G PCS ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guide

Chapter 14: Arria V GZ Transceiver Native PHY IP Core 14–2110G PCS ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide

Chapter 3: 10GBASE-R PHY IP Core 3–11Data InterfacesNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideData InterfacesTable 3–10

14–22 Chapter 14: Arria V GZ Transceiver Native PHY IP Core10G PCS ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guide

Chapter 14: Arria V GZ Transceiver Native PHY IP Core 14–2310G PCS ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide

14–24 Chapter 14: Arria V GZ Transceiver Native PHY IP Core10G PCS ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guide

Chapter 14: Arria V GZ Transceiver Native PHY IP Core 14–2510G PCS ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide

14–26 Chapter 14: Arria V GZ Transceiver Native PHY IP Core10G PCS ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guide

Chapter 14: Arria V GZ Transceiver Native PHY IP Core 14–2710G PCS ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide

14–28 Chapter 14: Arria V GZ Transceiver Native PHY IP Core10G PCS ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guide

Chapter 14: Arria V GZ Transceiver Native PHY IP Core 14–29InterfacesNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideGearboxT

14–30 Chapter 14: Arria V GZ Transceiver Native PHY IP CoreCommon Interface PortsAltera Transceiver PHY IP Core November 2012 Altera CorporationUser G

Chapter 14: Arria V GZ Transceiver Native PHY IP Core 14–31Common Interface PortsNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser G

3–12 Chapter 3: 10GBASE-R PHY IP CoreData InterfacesAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideTable 3–11 provides the m

14–32 Chapter 14: Arria V GZ Transceiver Native PHY IP CoreCommon Interface PortsAltera Transceiver PHY IP Core November 2012 Altera CorporationUser G

Chapter 14: Arria V GZ Transceiver Native PHY IP Core 14–33Standard PCS Interface PortsNovember 2012 Altera Corporation Altera Transceiver PHY IP Core

14–34 Chapter 14: Arria V GZ Transceiver Native PHY IP CoreStandard PCS Interface PortsAltera Transceiver PHY IP Core November 2012 Altera Corporation

Chapter 14: Arria V GZ Transceiver Native PHY IP Core 14–35Standard PCS Interface PortsNovember 2012 Altera Corporation Altera Transceiver PHY IP Core

14–36 Chapter 14: Arria V GZ Transceiver Native PHY IP Core10G PCS InterfaceAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guide1

Chapter 14: Arria V GZ Transceiver Native PHY IP Core 14–3710G PCS InterfaceNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideT

14–38 Chapter 14: Arria V GZ Transceiver Native PHY IP Core10G PCS InterfaceAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guidet

Chapter 14: Arria V GZ Transceiver Native PHY IP Core 14–3910G PCS InterfaceNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideR

14–40 Chapter 14: Arria V GZ Transceiver Native PHY IP Core10G PCS InterfaceAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guider

Chapter 14: Arria V GZ Transceiver Native PHY IP Core 14–4110G PCS InterfaceNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guider

Chapter 3: 10GBASE-R PHY IP Core 3–13Status, 1588, and PLL Reference Clock InterfacesNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUs

14–42 Chapter 14: Arria V GZ Transceiver Native PHY IP Core10G PCS InterfaceAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guidet

Chapter 14: Arria V GZ Transceiver Native PHY IP Core 14–4310G PCS InterfaceNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guider

14–44 Chapter 14: Arria V GZ Transceiver Native PHY IP CoreSDC Timing ConstraintsAltera Transceiver PHY IP Core November 2012 Altera CorporationUser G

Chapter 14: Arria V GZ Transceiver Native PHY IP Core 14–45Dynamic ReconfigurationNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser

14–46 Chapter 14: Arria V GZ Transceiver Native PHY IP CoreSimulation SupportAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guide

November 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide15. Cyclone V Transceiver Native PHY IPCoreThe Cyclone V Transceiver Native P

15–2 Chapter 15: Cyclone V Transceiver Native PHY IP CoreDevice Family SupportAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guid

Chapter 15: Cyclone V Transceiver Native PHY IP Core 15–3General ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideGe

15–4 Chapter 15: Cyclone V Transceiver Native PHY IP CorePMA ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuidePMA Pa

Chapter 15: Cyclone V Transceiver Native PHY IP Core 15–5PMA ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideTX PLL

3–14 Chapter 3: 10GBASE-R PHY IP CoreClocks for Arria V GT DevicesAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideClocks for

15–6 Chapter 15: Cyclone V Transceiver Native PHY IP CorePMA ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideRX PMA

Chapter 15: Cyclone V Transceiver Native PHY IP Core 15–7PMA ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideTable

15–8 Chapter 15: Cyclone V Transceiver Native PHY IP CoreStandard PCS ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Gu

Chapter 15: Cyclone V Transceiver Native PHY IP Core 15–9Standard PCS ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Gu

15–10 Chapter 15: Cyclone V Transceiver Native PHY IP CoreStandard PCS ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser G

Chapter 15: Cyclone V Transceiver Native PHY IP Core 15–11Standard PCS ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser G

15–12 Chapter 15: Cyclone V Transceiver Native PHY IP CoreStandard PCS ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser G

Chapter 15: Cyclone V Transceiver Native PHY IP Core 15–13Standard PCS ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser G

15–14 Chapter 15: Cyclone V Transceiver Native PHY IP CoreStandard PCS ParametersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser G

Chapter 15: Cyclone V Transceiver Native PHY IP Core 15–15Standard PCS ParametersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser G

Chapter 3: 10GBASE-R PHY IP Core 3–15Clocks for Arria V GZ DevicesNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideClocks for

15–16 Chapter 15: Cyclone V Transceiver Native PHY IP CoreInterfacesAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideInterface

Chapter 15: Cyclone V Transceiver Native PHY IP Core 15–17Common Interface PortsNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Gu

15–18 Chapter 15: Cyclone V Transceiver Native PHY IP CoreStandard PCS Interface PortsAltera Transceiver PHY IP Core November 2012 Altera CorporationU

Chapter 15: Cyclone V Transceiver Native PHY IP Core 15–19Standard PCS Interface PortsNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreU

15–20 Chapter 15: Cyclone V Transceiver Native PHY IP CoreStandard PCS Interface PortsAltera Transceiver PHY IP Core November 2012 Altera CorporationU

Chapter 15: Cyclone V Transceiver Native PHY IP Core 15–21SDC Timing ConstraintsNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Gu

15–22 Chapter 15: Cyclone V Transceiver Native PHY IP CoreSDC Timing ConstraintsAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Gu

Chapter 15: Cyclone V Transceiver Native PHY IP Core 15–23Dynamic ReconfigurationNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser G

15–24 Chapter 15: Cyclone V Transceiver Native PHY IP CoreSimulation SupportAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guide

November 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide16. Transceiver ReconfigurationController IP CoreThe Altera Transceiver Reco

3–16 Chapter 3: 10GBASE-R PHY IP CoreClocks for Stratix IV DevicesAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideThe PCS run

16–2 Chapter 16: Transceiver Reconfiguration Controller IP CoreAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideThis user guid

Chapter 16: Transceiver Reconfiguration Controller IP Core 16–3System OverviewNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guid

16–4 Chapter 16: Transceiver Reconfiguration Controller IP CoreDevice Family SupportAltera Transceiver PHY IP Core November 2012 Altera CorporationUse

Chapter 16: Transceiver Reconfiguration Controller IP Core 16–5Performance and Resource UtilizationNovember 2012 Altera Corporation Altera Transceiver

16–6 Chapter 16: Transceiver Reconfiguration Controller IP CoreParameterizing the Transceiver Reconfiguration Controller IP Core in QsysAltera Transce

Chapter 16: Transceiver Reconfiguration Controller IP Core 16–7Parameterizing the Transceiver Reconfiguration Controller IP Core in QsysNovember 2012

16–8 Chapter 16: Transceiver Reconfiguration Controller IP CoreInterfacesAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideInte

Chapter 16: Transceiver Reconfiguration Controller IP Core 16–9InterfacesNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideTran

16–10 Chapter 16: Transceiver Reconfiguration Controller IP CoreInterfacesAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guidepro

Chapter 16: Transceiver Reconfiguration Controller IP Core 16–11Transceiver Reconfiguration Controller Memory MapNovember 2012 Altera Corporation Alte

Chapter 3: 10GBASE-R PHY IP Core 3–17Clocks for Stratix V DevicesNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideClocks for S

16–12 Chapter 16: Transceiver Reconfiguration Controller IP CoreTransceiver Reconfiguration Controller Calibration FunctionsAltera Transceiver PHY IP

Chapter 16: Transceiver Reconfiguration Controller IP Core 16–13PMA Analog Control RegistersNovember 2012 Altera Corporation Altera Transceiver PHY IP

16–14 Chapter 16: Transceiver Reconfiguration Controller IP CoreEyeQ RegistersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guid

Chapter 16: Transceiver Reconfiguration Controller IP Core 16–15EyeQ RegistersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guid

16–16 Chapter 16: Transceiver Reconfiguration Controller IP CoreDFE RegistersAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guide

Chapter 16: Transceiver Reconfiguration Controller IP Core 16–17DFE RegistersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide

16–18 Chapter 16: Transceiver Reconfiguration Controller IP CoreControlling DFE Using Register-Based ReconfigurationAltera Transceiver PHY IP Core Nov

Chapter 16: Transceiver Reconfiguration Controller IP Core 16–19Turning on DFE One-Time Adaptation ModeNovember 2012 Altera Corporation Altera Transce

16–20 Chapter 16: Transceiver Reconfiguration Controller IP CoreSetting the First Tap Value Using DFE in Manual ModeAltera Transceiver PHY IP Core Nov

Chapter 16: Transceiver Reconfiguration Controller IP Core 16–21AEQ RegistersNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide

iv ContentsContentsAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideFunctional Description . . . . . . . . . . . . . . . . .

3–18 Chapter 3: 10GBASE-R PHY IP CoreRegister Interface and Register DescriptionsAltera Transceiver PHY IP Core November 2012 Altera CorporationUser G

16–22 Chapter 16: Transceiver Reconfiguration Controller IP CoreATX PLL Calibration RegistersAltera Transceiver PHY IP Core November 2012 Altera Corpo

Chapter 16: Transceiver Reconfiguration Controller IP Core 16–23PLL ReconfigurationNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser

16–24 Chapter 16: Transceiver Reconfiguration Controller IP CorePLL ReconfigurationAltera Transceiver PHY IP Core November 2012 Altera CorporationUser

Chapter 16: Transceiver Reconfiguration Controller IP Core 16–25PLL Reconfiguration RegistersNovember 2012 Altera Corporation Altera Transceiver PHY I

16–26 Chapter 16: Transceiver Reconfiguration Controller IP CoreChannel and PLL ReconfigurationAltera Transceiver PHY IP Core November 2012 Altera Cor

Chapter 16: Transceiver Reconfiguration Controller IP Core 16–27Channel and PLL ReconfigurationNovember 2012 Altera Corporation Altera Transceiver PHY

16–28 Chapter 16: Transceiver Reconfiguration Controller IP CoreStreamer Module RegistersAltera Transceiver PHY IP Core November 2012 Altera Corporati

Chapter 16: Transceiver Reconfiguration Controller IP Core 16–29Streamer Module RegistersNovember 2012 Altera Corporation Altera Transceiver PHY IP Co

16–30 Chapter 16: Transceiver Reconfiguration Controller IP CoreStreamer Module RegistersAltera Transceiver PHY IP Core November 2012 Altera Corporati

Chapter 16: Transceiver Reconfiguration Controller IP Core 16–31MIF GenerationNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guid

Chapter 3: 10GBASE-R PHY IP Core 3–19Register Interface and Register DescriptionsNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser G

16–32 Chapter 16: Transceiver Reconfiguration Controller IP CoreMIF FormatAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideYou

Chapter 16: Transceiver Reconfiguration Controller IP Core 16–33xcvr_diffmifgen UtilityNovember 2012 Altera Corporation Altera Transceiver PHY IP Core

16–34 Chapter 16: Transceiver Reconfiguration Controller IP Corexcvr_diffmifgen UtilityAltera Transceiver PHY IP Core November 2012 Altera Corporation

Chapter 16: Transceiver Reconfiguration Controller IP Core 16–35Reduced MIF CreationNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUse

16–36 Chapter 16: Transceiver Reconfiguration Controller IP CoreChanging Transceiver Settings Using Register-Based ReconfigurationAltera Transceiver P

Chapter 16: Transceiver Reconfiguration Controller IP Core 16–37Changing Transceiver Settings Using Register-Based ReconfigurationNovember 2012 Altera

16–38 Chapter 16: Transceiver Reconfiguration Controller IP CoreChanging Transceiver Settings Using Streamer-Based ReconfigurationAltera Transceiver P

Chapter 16: Transceiver Reconfiguration Controller IP Core 16–39Changing Transceiver Settings Using Streamer-Based ReconfigurationNovember 2012 Altera

16–40 Chapter 16: Transceiver Reconfiguration Controller IP CoreChanging Transceiver Settings Using Streamer-Based ReconfigurationAltera Transceiver P

Chapter 16: Transceiver Reconfiguration Controller IP Core 16–41Understanding Logical Channel NumberingNovember 2012 Altera Corporation Altera Transce

3–20 Chapter 3: 10GBASE-R PHY IP CoreRegister Interface and Register DescriptionsAltera Transceiver PHY IP Core November 2012 Altera CorporationUser G

16–42 Chapter 16: Transceiver Reconfiguration Controller IP CoreUnderstanding Logical Channel NumberingAltera Transceiver PHY IP Core November 2012 Al

Chapter 16: Transceiver Reconfiguration Controller IP Core 16–43Understanding Logical Channel NumberingNovember 2012 Altera Corporation Altera Transce

16–44 Chapter 16: Transceiver Reconfiguration Controller IP CoreUnderstanding Logical Channel NumberingAltera Transceiver PHY IP Core November 2012 Al

Chapter 16: Transceiver Reconfiguration Controller IP Core 16–45Understanding Logical Channel NumberingNovember 2012 Altera Corporation Altera Transce

16–46 Chapter 16: Transceiver Reconfiguration Controller IP CoreUnderstanding Logical Channel NumberingAltera Transceiver PHY IP Core November 2012 Al

Chapter 16: Transceiver Reconfiguration Controller IP Core 16–47Transceiver Reconfiguration Controller to PHY IP ConnectivityNovember 2012 Altera Corp

16–48 Chapter 16: Transceiver Reconfiguration Controller IP CoreMerging TX PLLs In Multiple Transceiver PHY InstancesAltera Transceiver PHY IP Core No

Chapter 16: Transceiver Reconfiguration Controller IP Core 16–49Loopback ModesNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guid

16–50 Chapter 16: Transceiver Reconfiguration Controller IP CoreLoopback ModesAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guid

November 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide17. Transceiver PHY Reset Controller IPCoreThe Transceiver PHY Reset Controll

Chapter 3: 10GBASE-R PHY IP Core 3–21Dynamic Reconfiguration for Stratix IV DevicesNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser

Chapter 17: Transceiver PHY Reset Controller IP Core 17–2Device Family SupportNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guid

Chapter 17: Transceiver PHY Reset Controller IP Core 17–3Performance and Resource UtilizationNovember 2012 Altera Corporation Altera Transceiver PHY I

Chapter 17: Transceiver PHY Reset Controller IP Core 17–4Transceiver PHY Reset Controller ParametersNovember 2012 Altera Corporation Altera Transceive

Chapter 17: Transceiver PHY Reset Controller IP Core 17–5InterfacesNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideInterfaces

Chapter 17: Transceiver PHY Reset Controller IP Core 17–6InterfacesNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideTable 17–4

Chapter 17: Transceiver PHY Reset Controller IP Core 17–7InterfacesNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideresetInput

17–8 Chapter 17: Transceiver PHY Reset Controller IP CoreTiming Constraints for Reset Signals when Using Bonded PCS ChannelsAltera Transceiver PHY IP

November 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide18. Analog Parameters Set Using QSFAssignmentsYou specify the analog paramete

18–2 Chapter 18: Analog Parameters Set Using QSF AssignmentsAnalog Settings for Arria V DevicesAltera Transceiver PHY IP Core November 2012 Altera Cor

Chapter 18: Analog Parameters Set Using QSF Assignments 18–3Analog Settings for Arria V DevicesNovember 2012 Altera Corporation Altera Transceiver PHY

3–22 Chapter 3: 10GBASE-R PHY IP CoreTimeQuest Timing ConstraintsAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideTable 3–17 d

18–4 Chapter 18: Analog Parameters Set Using QSF AssignmentsAnalog Settings for Arria V DevicesAltera Transceiver PHY IP Core November 2012 Altera Cor

Chapter 18: Analog Parameters Set Using QSF Assignments 18–5Analog Settings for Arria V GZ DevicesNovember 2012 Altera Corporation Altera Transceiver

18–6 Chapter 18: Analog Parameters Set Using QSF AssignmentsAnalog Settings for Arria V GZ DevicesAltera Transceiver PHY IP Core November 2012 Altera

Chapter 18: Analog Parameters Set Using QSF Assignments 18–7Analog Settings for Arria V GZ DevicesNovember 2012 Altera Corporation Altera Transceiver

18–8 Chapter 18: Analog Parameters Set Using QSF AssignmentsAnalog Settings for Arria V GZ DevicesAltera Transceiver PHY IP Core November 2012 Altera

Chapter 18: Analog Parameters Set Using QSF Assignments 18–9Analog Settings for Arria V GZ DevicesNovember 2012 Altera Corporation Altera Transceiver

18–10 Chapter 18: Analog Parameters Set Using QSF AssignmentsAnalog Settings for Cyclone V DevicesAltera Transceiver PHY IP Core November 2012 Altera

Chapter 18: Analog Parameters Set Using QSF Assignments 18–11Analog Settings for Cyclone V DevicesNovember 2012 Altera Corporation Altera Transceiver

18–12 Chapter 18: Analog Parameters Set Using QSF AssignmentsAnalog Settings for Cyclone V DevicesAltera Transceiver PHY IP Core November 2012 Altera

Chapter 18: Analog Parameters Set Using QSF Assignments 18–13Analog Settings for Stratix V DevicesNovember 2012 Altera Corporation Altera Transceiver

Chapter 3: 10GBASE-R PHY IP Core 3–23TimeQuest Timing ConstraintsNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide#***********

18–14 Chapter 18: Analog Parameters Set Using QSF AssignmentsAnalog Settings for Stratix V DevicesAltera Transceiver PHY IP Core November 2012 Altera

Chapter 18: Analog Parameters Set Using QSF Assignments 18–15Analog Settings for Stratix V DevicesNovember 2012 Altera Corporation Altera Transceiver

18–16 Chapter 18: Analog Parameters Set Using QSF AssignmentsAnalog Settings for Stratix V DevicesAltera Transceiver PHY IP Core November 2012 Altera

Chapter 18: Analog Parameters Set Using QSF Assignments 18–17Analog Settings for Stratix V DevicesNovember 2012 Altera Corporation Altera Transceiver

18–18 Chapter 18: Analog Parameters Set Using QSF AssignmentsAnalog Settings for Stratix V DevicesAltera Transceiver PHY IP Core November 2012 Altera

November 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide19. Migrating from Stratix IV to Stratix VDevicesPreviously, Altera provided

19–2 Chapter 19: Migrating from Stratix IV to Stratix V DevicesDifferences in Dynamic Reconfiguration for Stratix IV and Stratix V TransceiversAltera

Chapter 19: Migrating from Stratix IV to Stratix V Devices 19–3Differences Between XAUI PHY Parameters for Stratix IV and Stratix V DevicesNovember 20

19–4 Chapter 19: Migrating from Stratix IV to Stratix V DevicesDifferences Between XAUI PHY Ports in Stratix IV and Stratix V DevicesAltera Transceive

Chapter 19: Migrating from Stratix IV to Stratix V Devices 19–5Differences Between PHY IP Core for PCIe PHY (PIPE) Parameters in Stratix IV and Strati

3–24 Chapter 3: 10GBASE-R PHY IP CoreTimeQuest Timing ConstraintsAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guide1 This .sdc

19–6 Chapter 19: Migrating from Stratix IV to Stratix V DevicesDifferences Between PHY IP Core for PCIe PHY (PIPE) for Stratix IV and Stratix V Device

Chapter 19: Migrating from Stratix IV to Stratix V Devices 19–7Differences Between PHY IP Core for PCIe PHY (PIPE) for Stratix IV and Stratix V Device

19–8 Chapter 19: Migrating from Stratix IV to Stratix V DevicesDifferences Between PHY IP Core for PCIe PHY (PIPE) for Stratix IV and Stratix V Device

Chapter 19: Migrating from Stratix IV to Stratix V Devices 19–9Differences Between Custom PHY Parameters for Stratix IV and Stratix V DevicesNovember

19–10 Chapter 19: Migrating from Stratix IV to Stratix V DevicesDifferences Between Custom PHY Ports in Stratix IV and Stratix V DevicesAltera Transce

Chapter 19: Migrating from Stratix IV to Stratix V Devices 19–11Differences Between Custom PHY Ports in Stratix IV and Stratix V DevicesNovember 2012

19–12 Chapter 19: Migrating from Stratix IV to Stratix V DevicesDifferences Between Custom PHY Ports in Stratix IV and Stratix V DevicesAltera Transce

November 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideAdditional InformationThis chapter provides additional information about the

20–2 Additional InformationAdditional InformationRevision HistoryAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuidePHY IP Core

Additional InformationAdditional Information 20–3Revision HistoryNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideCyclone V Tr

Chapter 3: 10GBASE-R PHY IP Core 3–25Simulation Files and Example TestbenchNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideSi

20–4 Additional InformationAdditional InformationRevision HistoryAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guide10GBASE-RJun

Additional InformationAdditional Information 20–5Revision HistoryNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideInterlakenJu

20–6 Additional InformationAdditional InformationRevision HistoryAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideCustom Trans

Additional InformationAdditional Information 20–7Revision HistoryNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideDeterministi

20–8 Additional InformationAdditional InformationRevision HistoryAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guide10GBASE-RFeb

Additional InformationAdditional Information 20–9Revision HistoryNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideInterlakenDe

20–10 Additional InformationAdditional InformationRevision HistoryAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideIntroductio

Additional InformationAdditional Information 20–11Revision HistoryNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideLow Latency

20–12 Additional InformationAdditional InformationRevision HistoryAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideMay 2011 1.

Additional InformationAdditional Information 20–13Revision HistoryNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideInterlaken

3–26 Chapter 3: 10GBASE-R PHY IP CoreSimulation Files and Example TestbenchAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guide

20–14 Additional InformationAdditional InformationRevision HistoryAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideTransceiver

Additional InformationAdditional Information 20–15Revision HistoryNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideXAUI PHY Tr

20–16 Additional InformationAdditional InformationHow to Contact AlteraAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideHow to

Additional InformationAdditional Information 20–17Typographic ConventionsNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guideital

20–18 Additional InformationAdditional InformationTypographic ConventionsAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guide

November 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide4. Backplane Ethernet 10GBASE-KR PHYIP CoreThe Backplane Ethernet 10GBASE-KR

ContentsContents vNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideChapter 6. XAUI PHY IP CoreRelease Information . . . . .

Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core 4–2Release InformationNovember 2012 Altera CorporationAltera Transceiver PHY IP CoreUser Guide1 F

Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core 4–3Performance and Resource UtilizationNovember 2012 Altera CorporationAltera Transceiver PHY IP

Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core 4–4Link Training Parameters and Auto-Negotiation ParametersNovember 2012 Altera CorporationAltera

Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core 4–5Parameters and Speed Negotiation ParametersNovember 2012 Altera CorporationAltera Transceiver

Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core 4–6Parameters and Speed Negotiation ParametersNovember 2012 Altera CorporationAltera Transceiver

Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core 4–7Analog ParametersNovember 2012 Altera CorporationAltera Transceiver PHY IP CoreUser GuideAnalo

Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core 4–8Functional DescriptionNovember 2012 Altera CorporationAltera Transceiver PHY IP CoreUser Guide

Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core 4–9Functional DescriptionNovember 2012 Altera CorporationAltera Transceiver PHY IP CoreUser Guide

Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core 4–10InterfacesNovember 2012 Altera CorporationAltera Transceiver PHY IP CoreUser GuideInterfacesF

Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core 4–11Clock and Reset InterfacesNovember 2012 Altera CorporationAltera Transceiver PHY IP CoreUser

ContentsContents viNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideSerial Data Interface . . . . . . . . . . . . . . . . . .

Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core 4–12Data InterfacesNovember 2012 Altera CorporationAltera Transceiver PHY IP CoreUser GuideTable

Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core 4–13Data InterfacesNovember 2012 Altera CorporationAltera Transceiver PHY IP CoreUser GuideThe 10

Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core 4–14Data InterfacesNovember 2012 Altera CorporationAltera Transceiver PHY IP CoreUser GuideThe 72

Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core 4–15Control and Status InterfacesNovember 2012 Altera CorporationAltera Transceiver PHY IP CoreUs

Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core 4–16PHY Link TrainingNovember 2012 Altera CorporationAltera Transceiver PHY IP CoreUser GuidePHY

Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core 4–17Daisy-Chain ModeNovember 2012 Altera CorporationAltera Transceiver PHY IP CoreUser GuideDaisy

Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core 4–18Embedded Processor Mode InterfaceNovember 2012 Altera CorporationAltera Transceiver PHY IP Co

Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core 4–19Register Interface and Register DescriptionsNovember 2012 Altera CorporationAltera Transceive

Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core 4–20Register Interface and Register DescriptionsNovember 2012 Altera CorporationAltera Transceive

Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core 4–21Register Interface and Register DescriptionsNovember 2012 Altera CorporationAltera Transceive

ContentsContents viiNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideChapter 11. Deterministic Latency PHY IP CoreAuto-Negotia

Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core 4–22Register Interface and Register DescriptionsNovember 2012 Altera CorporationAltera Transceive

Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core 4–23Register Interface and Register DescriptionsNovember 2012 Altera CorporationAltera Transceive

Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core 4–24Register Interface and Register DescriptionsNovember 2012 Altera CorporationAltera Transceive

Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core 4–25Register Interface and Register DescriptionsNovember 2012 Altera CorporationAltera Transceive

Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core 4–26Register Interface and Register DescriptionsNovember 2012 Altera CorporationAltera Transceive

Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core 4–27Register Interface and Register DescriptionsNovember 2012 Altera CorporationAltera Transceive

4–28 Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP CoreRegister Interface and Register DescriptionsAltera Transceiver PHY IP Core November 2012 Alte

Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core 4–29Register Interface and Register DescriptionsNovember 2012 Altera CorporationAltera Transceive

4–30 Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP CoreRegister Interface and Register DescriptionsAltera Transceiver PHY IP Core November 2012 Alte

Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core 4–3110GBASE-KR PHY PMA and PCS RegistersNovember 2012 Altera CorporationAltera Transceiver PHY IP

viii ContentsContentsAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideCommon Interface Ports . . . . . . . . . . . . . . . . .

4–32 Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core10GBASE-KR PHY 1GbE RegistersAltera Transceiver PHY IP Core November 2012 Altera CorporationU

Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core 4–33Dynamic Reconfiguration from 1G to 10GbENovember 2012 Altera CorporationAltera Transceiver PH

4–34 Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP CoreDynamic Reconfiguration from 1G to 10GbEAltera Transceiver PHY IP Core November 2012 Altera C

Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core 4–35Creating a 10GBASE-KR DesignNovember 2012 Altera CorporationAltera Transceiver PHY IP CoreUse

4–36 Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP CoreEditing a MIF FileAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guide8.

Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core 4–37Design ExamplesNovember 2012 Altera CorporationAltera Transceiver PHY IP CoreUser GuideDesign

4–38 Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP CoreAcronymsAltera Transceiver PHY IP Core November 2012 Altera CorporationUser GuideAcronymsTabl

Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP Core 4–39AcronymsNovember 2012 Altera CorporationAltera Transceiver PHY IP CoreUser GuideWAN Wide Area

4–40 Chapter 4: Backplane Ethernet 10GBASE-KR PHY IP CoreAcronymsAltera Transceiver PHY IP Core November 2012 Altera CorporationUser Guide

November 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide5. 1G/10 Gbps Ethernet PHY IP CoreThe 1G/10 Gbps Ethernet PHY MegaCore®(1G/10

ContentsContents ixNovember 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideInterlaken Frame Synchronizer . . . . . . . . . . . . .

Chapter 5: 1G/10 Gbps Ethernet PHY IP Core 5–21G/10GbE Release InformationNovember 2012 Altera CorporationAltera Transceiver PHY IP CoreUser GuideAn A

Chapter 5: 1G/10 Gbps Ethernet PHY IP Core 5–3Parameterizing the 1G/10GbE PHYNovember 2012 Altera CorporationAltera Transceiver PHY IP CoreUser Guidef

Chapter 5: 1G/10 Gbps Ethernet PHY IP Core 5–4Parameterizing the 1G/10GbE PHYNovember 2012 Altera CorporationAltera Transceiver PHY IP CoreUser Guide1

Chapter 5: 1G/10 Gbps Ethernet PHY IP Core 5–5Analog ParametersNovember 2012 Altera CorporationAltera Transceiver PHY IP CoreUser GuideSpeed Detection

Chapter 5: 1G/10 Gbps Ethernet PHY IP Core 5–6InterfacesNovember 2012 Altera CorporationAltera Transceiver PHY IP CoreUser GuideInterfacesFigure 5–2 s

Chapter 5: 1G/10 Gbps Ethernet PHY IP Core 5–7Clock and Reset InterfacesNovember 2012 Altera CorporationAltera Transceiver PHY IP CoreUser GuidePhy_mg

Chapter 5: 1G/10 Gbps Ethernet PHY IP Core 5–8Data InterfacesNovember 2012 Altera CorporationAltera Transceiver PHY IP CoreUser GuideData Interfaces T

Chapter 5: 1G/10 Gbps Ethernet PHY IP Core 5–9Data InterfacesNovember 2012 Altera CorporationAltera Transceiver PHY IP CoreUser GuideThe 72-bit TX XGM

Chapter 5: 1G/10 Gbps Ethernet PHY IP Core 5–10Control and Status InterfacesNovember 2012 Altera CorporationAltera Transceiver PHY IP CoreUser GuideTa

Chapter 5: 1G/10 Gbps Ethernet PHY IP Core 5–11Register Interface and Register DescriptionsNovember 2012 Altera CorporationAltera Transceiver PHY IP C