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3–8 Chapter 3: 10GBASE-R PHY IP Core

General Option Parameters

Altera Transceiver PHY IP Core November 2012 Altera Corporation

User Guide

Example 3–1 shows how to remove the restriction on logical channel 0 assignment in

Stratix V devices by redefining the

pma_bonding_master

parameter using the

Quartus II Assignment Editor. In this example, the

pma_bonding_master

was

originally assigned to physical channel 1. (The original assignment could also have

been to physical channel 4.) The

parameter reassigns the

pma_bonding_master

the 10GBASE-R instance name. You must substitute the instance name from your

design for the instance name shown in quotation marks.

Reference Clock Frequency

322.265625 MHz

644.53125 MHz

Arria V and Stratix V devices support both frequencies. Stratix IV GT

devices only support 644.53125 MHz.

Additional Options

Enable additional control and

status pins

On/Off

If you turn this option On, the following 2 signals are brought out to

the top level of the IP core to facilitate debugging:

rx_hi_ber

and

rx_block_lock

Enable rx_recovered_clk pin On/Off

When you turn this option On, the RX recovered clock signal is an

output signal.

Enable pll_locked status port On/Off

For Arria V and Stratix V devices:

When you turn this option On, a PLL locked status signal is included

as a top-level signal of the core.

Use external PMA control and

reconfig

On/Off

For Stratix IV devices:

If you turn this option on, the PMA controller and reconfiguration

block are external, rather than included in the 10GBASE-R PHY IP

Core, allowing you to use the same PMA controller and

reconfiguration IP cores for other protocols in the same transceiver

quad.

When you turn this option On, the

cal_blk_powerdown

(0x021)

and

pma_tx_pll_is_locked

(0x022) registers are available.

Enable rx_coreclkin port On/Off

When selected,

rx_coreclkin

is sourced from the 156.25 MHz

xgmii_rx_clk

signal avoiding the use of a FPLL to generate this

clock. This clock drives the read side of RX FIFO.

Starting channel number 0–96

For Stratix IV devices, specifies the starting channel number. Must be

0 or a multiple of 4. You only need to set this parameter if you are

using external PMA and reconfiguration modules.

Stratix V devices have different restrictions. Logical channel 0 should

be assigned to either physical transceiver channel 1 or channel 4 of a

transceiver bank. However, if you have already created a PCB with a

different lane assignment for logical channel 0, you can use the

workaound shown in Example 3–1 to remove this restriction.

Assignment of the starting channel number is required for serial

transceiver dynamic reconfiguration.

Enable IEEE 1588 latency

adjustment ports

On/Off

When you turn this option On, the core includes logic to implement

the IEEE 1588 Precision Time Protocol.

Table 3–8. General Options (Part 2 of 2)

Name Value Description

Example 3–1. Overriding Logical Channel 0 Channel Assignment Restrictions in Stratix V Devices for ×6 or ×N Bonding

set_parameter -name pma_bonding_master "\"1\"" -to "<PHY IP instance name>"

1 2 ... 25 26 27 28 29 30 31 32 33 34 35 ... 483 484

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