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Chapter 3: 10GBASE-R PHY IP Core 3–13
Status, 1588, and PLL Reference Clock Interfaces
November 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
Table 3–12 provides the mapping from the XGMII RX interface to the XGMII SDR
interface.
Status, 1588, and PLL Reference Clock Interfaces
Table 3–13 describes signals that provide status information.
Table 3–12. Mapping from XGMII RX Bus to the XGMII SDR Bus
Signal Name XGMII Signal Name Description
xgmii_rx_dc_[7:0] xgmii_sdr_data[7:0]
Lane 0 data
xgmii_rx_dc_[8] xgmii_sdr_ctrl[0]
Lane 0 control
xgmii_rx_dc_[16:9] xgmii_sdr_data[15:8]
Lane 1 data
xgmii_rx_dc_[17] xgmii_sdr_ctrl[1]
Lane 1 control
xgmii_rx_dc_[25:18] xgmii_sdr_data[23:16]
Lane 2 data
xgmii_rx_dc_[26] xgmii_sdr_ctrl[2]
Lane 2 control
xgmii_rx_dc_[34:27] xgmii_sdr_data[31:24]
Lane 3 data
xgmii_rx_dc_[35] xgmii_sdr_ctrl[3]
Lane 3 control
xgmii_rx_dc_[43:36] xgmii_sdr_data[39:32]
Lane 4 data
xgmii_rx_dc_[44] xgmii_sdr_ctrl[4]
Lane 4 control
xgmii_rx_dc_[52:45] xgmii_sdr_data[47:40]
Lane 5 data
xgmii_rx_dc_[53] xgmii_sdr_ctrl[5]
Lane 5 control
xgmii_rx_dc_[61:54] xgmii_sdr_data[55:48]
Lane 6 data
xgmii_rx_dc_[62] xgmii_sdr_ctrl[6]
Lane 6 control
xgmii_rx_dc_[70:63] xgmii_sdr_data[63:56]
Lane 7 data
xgmii_rx_dc_[71] xgmii_sdr_ctrl[7]
Lane 7 control
Table 3–13. 10GBASE-R Status, 1588, and PLL Reference Clock Outputs
Signal Name Direction Description
rx_block_lock
Output Asserted to indicate that the block synchronizer has established synchronization.
rx_hi_ber
Output
Asserted by the BER monitor block to indicate a Sync Header high bit error rate
greater than 10
-4
.
rx_recovered_clk[<
n>:0]
Output This is the RX clock, which is recovered from the received data stream.
pll_locked
Output When asserted, indicates that the TX PLL is locked.
IEEE 1588 Precision Time Protocol
rx_latency_adj_10g
[11:0]
Output
When you enable 1588, this signal outputs the real time latency in XGMII clock
cycles (156.25 MHz) for the RX PCS and PMA datapath for 1G mode.
tx_latency_adj_10g
[11:0]
Output
When you enable 1588, this signal outputs real time latency in XGMII clock
cycles (156.25 MHz) for the TX PCS and PMA datapath for 1G mode.
PLL Reference Clock
pll_ref_clk
Input
For Stratix IV GT devices, the TX PLL reference clock must be 644.53125 MHz.
For Arria V and Stratix V devices, the TX PLL reference clock can be either
644.53125 MHz or 322.265625 MHz.
- User Guide 1
- Contents 3
- Chapter 6. XAUI PHY IP Core 5
- Chapter 9. Custom PHY IP Core 6
- ContentsContents vii 7
- ContentsContents ix 9
- Additional Information 11
- 1. Introduction 13
- 1–2 Chapter 1: Introduction 14
- Avalon-MM PHY Management 15
- 1–4 Chapter 1: Introduction 16
- Chapter 1: Introduction 1–5 17
- Unsupported Features 18
- 2. Getting Started 19
- Specifying Parameters 20
- Simulate the IP Core 22
- 3. 10GBASE-R PHY IP Core 23
- 10GBASE-R protocol 24
- Arria V GT 10GBASE-R 25
- Transceiver Protocol 25
- General Option Parameters 29
- Interfaces 32
- Clocks for Arria V GT Devices 36
- Clocks for Arria V GZ Devices 37
- Clocks for Stratix IV Devices 37
- Clocks for Stratix V Devices 39
- 10GBASE-R PHY IP Core 47
- Note to Table 4–3: 51
- Speed Detection 54
- Functional Description 56
- Clock and Reset Interfaces 59
- SDR XGMII interface: 62
- Control and Status Interfaces 63
- PHY Link Training 64
- Daisy-Chain Mode 65
- 10GBASE-KR PHY 1GbE Registers 80
- Creating a 10GBASE-KR Design 83
- WAN Wide Area Network 87
- Acronym Definition 87
- 1G/10GbE Release Information 90
- 10GBASE-R Parameters 92
- 1Gb Ethernet Parameters 92
- 1G/10GbE Registers 100
- PMA Registers 101
- PCS Registers 102
- GMII PCS Registers 103
- Sequencer 106
- Cntl & 106
- Creating a 1G/10GbE Design 107
- Editing a MIF File 108
- Design Examples 109
- Dynamic Reconfiguration 110
- Simulation 111
- TimeQuest Timing Constraints 111
- Acronyms 111
- 6. XAUI PHY IP Core 113
- Release Information 114
- Device Family Support 114
- Devices 115
- Parameterizing the XAUI PHY 115
- General Parameters 116
- Analog Parameters 117
- Stratix IV Devices 118
- Advanced Options Parameters 119
- Configurations 120
- Data Interfaces 122
- SDR XGMII TX Interface 124
- SDR XGMII RX Interface 124
- XAUI Hard IP Core 125
- Hard PCS 125
- Soft PCS 125
- TimeQuest Timing Cons 135
- Interlaken PHY IP Core 137
- Optional Port Parameters 140
- Interfaces 141
- Avalon-ST TX Interface 142
- Avalon-ST RX Interface 144
- TX and RX Serial Interface 147
- PLL Interface 147
- Optional Clocks for Deskew 148
- Resource Utilization 154
- General Options Parameters 155
- s window for Gen1 or Gen2 160
- s window for Gen1 160
- Figure 8–4 illustrates the 162
- Optional Status Interface 163
- Serial Data Interface 164
- PHY IP Core for PCI Express 165
- Hard PCS and PMA 165
- Phase 2 (Optional) 170
- Phase 3 (Optional) 171
- 9. Custom PHY IP Core 175
- Custom PHY IP Core 176
- Stratix V FPGA 176
- Word Alignment Parameters 181
- Rate Match FIFO Parameters 182
- Byte Order Parameters 183
- SOP to a different byte lane 184
- IP Core 186
- Presets for Ethernet 187
- RX interface 190
- Clock Interface 191
- Custom PHY PCS and PMA 193
- 10. Low Latency PHY IP Core 199
- (PCS-PMA interface width) 202
- Additional Options Parameters 203
- PMA and Light-Weight PCS 210
- Auto-Negotiation 216
- Note to Figure11–2: 217
- Delay Estimation Logic 219
- Delay Numbers 220
- the number of bits 230
- Deterministic PHY IP Core 232
- Parameter Presets 241
- PMA Parameters 243
- TX PMA Parameters 244
- TX PLL<n> 245
- RX CDR Options 246
- PMA Optional Ports 246
- Standard PCS Parameters 249
- Phase Compensation FIFO 250
- Rate Match FIFO 253
- 10G PCS Parameters 257
- 10G TX FIFO 258
- Stratix V Devices 259
- 100 ppm 260
- Interlaken Frame Generator 262
- Interlaken Frame Synchronizer 263
- s period 265
- s period, the 265
- 64b/66b Encoder and Decoder 266
- 96-bit bound. It adds the 67 267
- Common Interface Ports 270
- Standard PCS Interface Ports 273
- 10G PCS Interface 276
- SDC Timing Constraints 284
- Simulation Support 286
- RX PMA Parameters 292
- Arria V Devices 299
- Cyclone V Devices 368
- Controller IP Core 379
- Altera V-Series FPGA 381
- 500 400 0 0 100 383
- 4.9152 Gbps 387
- Embedded 389
- Controller 389
- Offset Cancellation 390
- Duty Cycle Calibration 390
- PMA Analog Control Registers 391
- 7’h0C [6:0] RW 391
- EyeQ Registers 392
- DFE Registers 394
- (Part 1 of 2) 395
- address to 0x0 396
- (Part 2 of 2) 396
- address of 0xB 397
- AEQ Registers 399
- ATX PLL Calibration Registers 400
- PLL Reconfiguration 401
- Transceiver PHYs 402
- PLL Reconfiguration Registers 403
- 7’h44 [15:0] RW 403
- Channel Reconfiguration 405
- Streamer Module Registers 406
- register address is invalid 406
- When the 407
- register specifies a 407
- register. When 407
- register 408
- MIF Generation 409
- MIF Format 410
- Arguments: 412
- -h: Displays help 412
- Reduced MIF Creation 413
- Register-Based Write 414
- Register-Based Read 415
- Figure 16–6. Sample MIF 418
- Example 16–11. (continued) 419
- Loopback Modes 427
- Transceiver 428
- Transceiver PHY Instance 429
- Transceiver PHY 429
- Reset Controller 429
- Assignments 437
- register to enable the 455
- Transceivers 456
- Stratix V GX/GS devices 458
- Note to Table 19–3: 459
- Note to Table 19–5: 462
- Note to Table 19–7: 465
- Revision History 468
- s for Gen2 operation 476
- address 480
- Note to Table: 482
- Typographic Conventions 483
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