Altera RapidIO II MegaCore Function Manual de usuario Pagina 79
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Chapter 4: Functional Description 4–37
Logical Layer Interfaces
August 2014 Altera Corporation RapidIO II MegaCore Function
User Guide
Port-Write Transmission
To send a RapidIO
MAINTENANCE
port-write packet to a remote device, you must
program the transmit port-write control and data registers. The
Tx Port
Write
Control
register is described in Table 6–45 on page 6–36 and the
Tx
Port
Write
Buffer
is described in Table 6–47 on page 6–37. You access these registers using the Register
Access Avalon-MM slave interface. You must program the values for the following
header fields in the corresponding fields in the
Tx
Port
Write
Control
register:
■
DESTINATION_ID
■
priority
■
wrsize
The RapidIO II IP core assigns the following values to the fields of the
MAINTENANCE
port-write
packet:
■ Assigns
ftype
the value of
4'b1000
■ Assigns
ttype
the value of
4'b0100
■ Calculates the values for the
wdptr
and
wrsize
fields of the transmitted packet
from the size of the
payload
to be sent, as defined by the
size
field of the
Tx
Port
Write
Control
register
■ Assigns the value of 0 to the Reserved
source_tid
and
config_offset
fields
The IP core creates the packet’s
payload
from the contents of the
Tx
Port
Write
Buffer
sequence of registers starting at register address
0x10210
. This buffer can store a
maximum of 64 bytes. The IP core starts the packet composition and transmission
process after you set the
PACKET_READY
bit in the
Tx
Port
Write
Control
register. The
RapidIO II IP core composes the
Maintenance port-write
packet and transmits it on
the RapidIO link.
Port-Write Reception
When the RapidIO II IP core Maintenance module receives a
MAINTENANCE
port-write
request packet (
ftype
has the value of 4’b1000 and
ttype
has the value of 4’b0100)
from the Transport layer, it extracts information from the packet header and uses the
information to write to registers
Rx
Port
Write
Control
(Table 6–48 on page 6–37)
through
Rx
Port
Write
Buffer
(Table 6–50 on page 6–37). The Maintenance module
extracts information from the following fields:
■
wrsize
— the values in the w
rsize
and
wdptr
packet fields determine the value of
the
PAYLOAD_SIZE
field in the
Rx Port Write Status
register (Table 6–49 on
page 6–37).
■
wdptr
— the values in the w
rsize
and
wdptr
packet fields determine the value of
the
PAYLOAD_SIZE
field in the
Rx Port Write Status
register (Table 6–49 on
page 6–37).
■
payload
— the Maintenance module copies the value of the
payload
packet field to
the
Rx
Port
Write Buffer
starting at register address
0x10260
. This buffer holds a
maximum of 64 bytes.
While the IP core is writing the
payload
to the buffer, it holds the
PORT_WRITE_BUSY
bit
of the
Rx
Port
Write
Status
register asserted. After the
payload
is completely written
to the buffer, if you have set the
RX_PACKET_STORED
bit of the
Maintenance Interrupt
Enable
register (Table 6–40 on page 6–35), the IP core asserts the interrupt signal
- User Guide 1
- RapidIO II MegaCore Function 1
- Contents 3
- Contents v 5
- Chapter 5. Signals 6
- Chapter 6. Software Interface 6
- Chapter 7. Testbench 6
- 1. About The RapidIO II 9
- MegaCore Function 9
- Releases 10
- RapidIO II IP Core Features 10
- Features 11
- Device Family Support 12
- IP Core Verification 13
- Hardware Testing 14
- Interoperability Testing 14
- Note to Table 1–3: 16
- Notes to Table 1–4: 16
- Installation and Licensing 17
- 2. Getting Started 19
- Simulating IP Cores 22
- Transceiver Settings 26
- External Transceiver PLL 26
- 3. Parameter Settings 31
- Note to Table 3–1: 32
- Enable 16-Bit Device ID Width 33
- Logical Layer Settings 34
- Capability Registers Settings 35
- Device ID 36
- Vendor ID 36
- Revision ID 36
- Assembly ID 36
- Assembly Information CAR 37
- Enable Flow Control Support 38
- Enable Switch Support 38
- Number of Ports 38
- Port Number 39
- Maximum PDU 39
- Destination Operations CAR 40
- Port General Control CSR 40
- Port 0 Control CSR 41
- Lane n Status 0 CSR 41
- Extended Features Pointer CSR 41
- 4. Functional Description 43
- Note to Table 4–2: 44
- Clocking and Reset Structure 45
- Notes to Table 4–3: 46
- RapidIO II 47
- Transactions 55
- Notes to Table 4–6: 57
- Notes to Table 4–7: 59
- Note to Table 4–8: 59
- Note to Figure 4–9: 66
- Note to Table 4–10: 70
- Notes to Table 4–11: 71
- Table 6–60 on page 6–40 72
- Note to Table 4–12: 73
- Maintenance Module 74
- Maintenance Interface Signals 75
- Doorbell Module Block Diagram 86
- Preserving Transaction Order 87
- Doorbell Module Signals 88
- Generating a Doorbell Message 88
- Receiving a Doorbell Message 89
- Transaction ID Ranges 90
- Notes to Table 4–24: 92
- Note to Table 4–26: 94
- Note to Table 4–27: 95
- field 97
- User Receiving Write Request 100
- Logical Layer Interfaces 101
- Transport Layer 112
- Receiver 113
- Transmitter 114
- Physical Layer 115
- Physical Layer Interfaces 116
- Low-level Interface Receiver 116
- CRC Checking and Removal 117
- Protocol Violations 119
- Fatal Errors 119
- Maintenance Avalon-MM Slave 120
- Maintenance Avalon-MM Master 121
- Port-Write Reception Module 122
- Input/Output Avalon-MM Slave 122
- Input/Output Avalon-MM Master 123
- 5. Signals 125
- Physical Layer Signals 126
- Low Latency Signals 127
- Multicast Event Signals 128
- Chapter 5: Signals 5–5 129
- Note to Table 5–7: 130
- Chapter 5: Signals 5–7 131
- 5–8 Chapter 5: Signals 132
- Register-Related Signals 133
- Avalon-MM Interface Signals 133
- Note to Table 5–12: 134
- Chapter 5: Signals 5–11 135
- Note to Table 5–15: 136
- Error Reporting Signals 137
- 5–14 Chapter 5: Signals 138
- 6. Software Interface 139
- Memory Map 140
- Physical Layer Registers 144
- Note to Table 6–9: 147
- Note to Table 6–14: 154
- Note to Table 6–15: 158
- Note to Table 6–17: 160
- Note to Table 6–22: 164
- Note to Table 6–23: 164
- Note to Table 6–24: 165
- Note to Table 6–25: 165
- Note to Table 6–26: 166
- Note to Table 6–27: 167
- Notes to Table 6–28: 168
- Notes to Table 6–29: 169
- Note to Table 6–30: 169
- Note to Table 6–31: 169
- Notes to Table 6–32: 170
- Note to Table 6–34: 171
- Note to Table 6–35: 171
- Note to Table 6–36: 172
- Note to Table 6–37: 172
- Transmit Port-Write Registers 174
- Receive Port-Write Registers 175
- Note to Table 6–59: 178
- Error Management Registers 180
- Note to Table 6–66: 181
- Notes to Table 6–67: 183
- Notes to Table 6–70: 185
- Notes to Table 6–71: 185
- Doorbell Message Registers 191
- Note to Table 6–89: 193
- 7. Testbench 195
- 7–2 Chapter 7: Testbench 196
- Testbench Overview 196
- Testbench Sequence 197
- 7–4 Chapter 7: Testbench 198
- Chapter 7: Testbench 7–5 199
- SWRITE Transactions 200
- NREAD Transactions 200
- NWRITE_R Transactions 201
- NWRITE Transactions 202
- Doorbell Transactions 202
- Port-Write Transactions 203
- Testbench Completion 204
- Chapter 7: Testbench 7–11 205
- 7–12 Chapter 7: Testbench 206
- A. Initialization Sequence 207
- MegaCore Function v12.1 209
- Additional Information 213
- Info–2 Additional Information 214
- Document Revision History 214
- Additional Information Info–3 215
- Info–4 Additional Information 216
- Note to Table: 217
- Info–6 Additional Information 218
- Typographic Conventions 218
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