Altera Virtual JTAG IP Core Manual de usuario

Virtual JTAG Megafunction (sld_virtual_jtag)2014.03.19UG-SLDVRTLSubscribeSend FeedbackThe Virtual JTAG (SLD_VIRTUAL_JTAG) megafunction is an Altera®-p

The figure below shows the input and output ports of the virtual JTAG megafunction. The JTAG TAPcontroller outputs and TMS signals are used for inform

Output PortsTable 3: Output Ports for the Virtual JTAG MegafunctionCommentsDescriptionRequiredPort NameConnected directly to the TCKdevice pin. Shared

Table 5: Low-Level Virtual JTAG State SignalsCommentsDescriptionRequiredPort NameShared among all virtualJTAG instances.Indicates that the device JTAG

CommentsDescriptionRequiredPort NameShared among all virtualJTAG instances.Indicates that the device JTAGcontroller is in the Exit1_IRstate.Nojtag_sta

Design Flow of the Virtual JTAG MegafunctionDesigning with the Virtual JTAG megafunction includes the following processes:• Configuring the Virtual JT

Figure 8: Block Diagram of a Design with a Single Virtual JTAG InstantiationInferred by Instantiationof MegafunctionGlue Logic between VJI and User De

Table 7: Tcl Commands Used with the Virtual JTAG MegafunctionDescriptionArgumentsCommandPerform an IR shift operation to thevirtual JTAG instance spec

Each device_virtual_ir_shift command issues a USER1 instruction to the JTAG Instruction Registerfollowed by a DR shift containing the VIR value provid

Figure 9: Compilation ReportTable 8: Virtual JTAG Settings DescriptionDescriptionSettingInstance index of the virtual JTAG megafunction. Assignedat co

To use the Tcl API to query for the bit pattern in your design, use theshow_equivalent_device_ir_dr_shift argument with the device_virtual_ir_shift an

Examples of debugging applications include induced trigger conditions evaluated by a SignalTap®II LogicAnalyzer by exercising test signals connected t

four bits long, the minimum length for the VIR value field for all SLD nodes in the design is at least four bitsin length. The Quartus II Tcl API auto

HUB_FORCE_IR capture must be issued whenever you capture the VIR from a target SLD node that is differentthan the current active node. DR Scan Shift 1

TAP controller or the system logic. Both the JTAG TAP controller and the sld_hub controller are guaranteedto be in the Test Logic Reset state after fi

Page 4 defines the stimuli that are used during the simulation of your megafunction. A stimulus is eithera Data Register shift (DR shift) or an Instru

• The ir_in output port of the Virtual JTAG megafunction is the parallel output of the contents that getshifted into the virtual IR of the Virtual JTA

else tdo <= bypass_reg;endmoduleThe decode logic is produced by defining a wire load to be active high whenever the IR of the Virtual JTAGm

be edited for generating different stimuli, though the preferred way to specify stimuli for DR and IR scanshifts is to use the MegaWizard Plug-In Mana

• In a real system, each instance of the Virtual JTAG megafunction works independently. In simulation,multiple instances can work at the same time. Fo

Compiling the DesignYou can instantiate a maximum of 128 instances of the Virtual JTAG megafunction in a design. Aftercompilation, each instance has a

Figure 15: Logic Resources Utilizedsld_virtual_jtaginstancesRelated Information• Design Implementation and Optimization• VerificationThird-Party Synth

Typical Circumstances for UseDescriptionToolYou want to view and edit thecontents of either the instructioncache or data cache of a Nios®IIprocessor a

Table 10: USER1 and USER2 Instruction ValuesBinary PatternInstruction00 0000 1100USER000 0000 1110USER1The USER1 instruction targets the virtual IR of

The SLD_NODE_INFO register is used to determine the address mapping for Virtual JTAG instance in yourdesign. This register set is shifted out by issui

Table 14: SLD_NODE_INFO Register DescriptionsFunctionFieldIdentifies the version of the SLD nodeNode VersionIdentifies the type of NODE IP (0x8 for th

Figure 16: Functional Model Interaction between USER1 DR CHAIN and SLD Node VIRsTDI TDOADDR[n - 1..0] VIR_valuemsb lsbADDR[n - 1..0]ADDR[n - 1..0]SLD

jtag_state_cir, jtag_state_e1dr, jtag_state_e1ir, jtag_state_e2dr, jtag_state_e2ir, jtag_state_pdr,

jtag_state_uir : out std_logic; tck : out std_logic; tdi : out std_logic;

Figure 17: JTAG TAP Controller State MachineCAPTURE_DRSHIFT_DREXIT1_DRPAUSE_DREXIT2_DRUPDATE_DRCAPTURE_IRSHIFT_IREXIT1_IRPAUSE_IREXIT2_IRUPDATE_IRRUN_

Functional DescriptionTAP Controller StateThis is a hold state. Once entered, the controller remains inthis state as long as TMS is held low.Run-Test/

Table 16: Instruction Register ValuesFunctionInstruction Register ValueInstruction to write a single value to the write side logic of the DCFIFO.PUSHI

Figure 19: Read Side Logic for DCFIFO Design ExampleIR Decode/StateDecode LogicIR_registerStateInformationTDOTDOWrite_reqData[7:0]Write_clockRead_reqR

simple stimulus patterns to solicit a response from the design under test during run-time, including thefollowing applications:• To diagnose, sample,

Figure 20: Runtime ExecutionFigure 21: SignalTap II Logic Analyzer Capture Triggering on a Flush OperationVirtual JTAG Megafunction (sld_virtual_jtag)

Design Example: Offloading Hardwired Revision InformationThis example demonstrates how you can use a GUI to offload revision information that is hardw

Document Revision HistoryTable 18: Document Revision HistoryChangesVersionDateUpdated the description of the SLD_IR_WIDTH parameter inthe "Parame

JTAG Circuitry ArchitectureThe basic architecture of the JTAG circuitry consists of the following components:• A set of Data Registers (DRs)• An Instr

Figure 3: Functional Model of the JTAG CircuitryIR Shift RegistersIR Update RegistersDR Shift Register 1DR Update Register 1DR Shift Register 2DR Upda

Figure 4: System Level Debugging Infrastructure Functional ModelJTAG TapControllerTCTMTDTDFPGASLD NodeSLD NodeSLD NodeSLD NodeSLD HubUser’s Design(Cor

Figure 5: Extension of the JTAG Protocol for PLD ApplicationsIR Shift RegistersIR Update RegistersDR Shift Register 1DR Update Register 1USER 0 Data R

This state information, including a bank of enable signals, is forwarded to each of the SLD nodes. The SLDnodes perform the updates to the VIR and VDR