Altera RapidIO II MegaCore Function Manual de usuario descargar pdf (Pagina 45)

Chapter 4: Functional Description 4–3

Clocking and Reset Structure

August 2014 Altera Corporation RapidIO II MegaCore Function

User Guide

f More detailed information about the RapidIO interface specification is available from

the RapidIO Trade Association website at www.rapidio.org.

Clocking and Reset Structure

All RapidIO II IP core variations have the following clock inputs:

■ Avalon system clock (

sys_clk

)

■ Reference clock for the transceiver Tx PLL and Rx PLL (

tx_pll_refclk

). In Arria

10 variations, this clock port drives only the Rx PLL

■ Arria 10 device transceiver channel clocks (

tx_bonding_clocks_chN

)

The RapidIO II IP core provides the following two clock outputs from the transceiver:

■ Recovered data clock (

rx_clkout

)

■ Transceiver transmit-side clock (

tx_clkout

)

In addition, if you turn on Enable transceiver dynamic reconfiguration in the

RapidIO II parameter editor, the IP core includes a

reconfig_clk_chN

input clock to

clock the Arria 10 Native PHY dynamic reconfiguration interface for each lane

Avalon System Clock

The Avalon system clock,

sys_clk

, is an input to the RapidIO II IP core that drives the

Transport and Logical layer modules and most of the Physical layer module.

1 You must drive the

sys_clk

clock from the same source from which you drive the

tx_pll_refclk

input clock.

Reference Clock

The reference clock,

tx_pll_refclk

, is the incoming reference clock for the

transceiver’s PLL. You specify the reference clock frequency in the RapidIO II

parameter editor when you create the RapidIO II IP core instance.

The ability to program the frequency of the input reference clock allows you to use an

existing clock in your system as the reference clock for the RapidIO II IP core. This

reference clock can have any of a set of frequencies that the PLL in the transceiver can

convert to the required internal clock speed for the RapidIO II IP core baud rate. The

choices available to you for this frequency are determined by the baud rate and target

device family.

1 You must drive the

tx_pll_refclk

clock from the same source from which you drive

the

sys_clk

input clock and the TX PLL

pll_refclk0

input clock.

f For information about this clock, including recommended frequency range, refer to

the Native PHY IP Core and Altera Transceiver Reconfiguration Controller chapters

of the Altera Transceiver PHY IP Core User Guide or the PLL and Clock Networks

chapter and the Reconfiguration Interface and Dynamic Reconfiguration chapter of

the Arria 10 Transceiver PHY User Guide, depending on your target device.

1 2 ... 40 41 42 43 44 45 46 47 48 49 50 ... 217 218

Comentarios a estos manuales

Sin comentarios

Altera RapidIO II MegaCore Function Manual de usuario Pagina 45

Comentarios a estos manuales

Relacionado con productos y manuales para Instrumentos de medición Altera RapidIO II MegaCore Function