Altera RapidIO II MegaCore Function Manual de usuario Pagina 143
- Pagina / 218
- Tabla de contenidos
- MARCADORES
Valorado. / 5. Basado en revisión del cliente
Chapter 6: Software Interface 6–5
Memory Map
August 2014 Altera Corporation RapidIO II MegaCore Function
User Guide
Extended Features Space: Error Management Extensions
These registers are defined in the RapidIO Interconnect Specification Part 8: Error Management Extensions Specification
and described in “Error Management Registers” on page 6–42.
0x300
Error Management Extensions Block
Header
0x304
Reserved
0x308
Logical/Transport
Layer
Error
Detect
Logical/Transport layer
0x30C
Logical/Transport
Layer
Error Enable
0x310
Logical/Transport
Layer High Address
Capture
— Reserved — RapidIO II IP core
has only 34-bit RapidIO addressing
0x314
Logical/Transport
Layer Address
Capture
0x318
Logical/Transport
Layer
Device
ID
Capture
0x31C
Logical/Transport
Layer
Control
Capture
0x320–0x324
Reserved
0x328
Port-Write Target Device ID
Maintenance module
0x32C
Packet Time-to-Live
Physical layer
0x330–0x33C
Reserved
0x340
Port 0 Error Detect
0x344
Port 0 Error Rate Enable
0x348
Port 0 Attributes Capture
0x34C
Port 0 Packet/Control Symbol Capture
0
0x350
Port 0 Packet Capture 1
0x354
Port 0 Packet Capture 2
0x358
Port 0 Packet Capture 3
0x35C–0x364
Reserved
0x368
Port 0 Error Rate
Physical layer
0x36C
Port 0 Error Rate Threshold
Implementation-Defined Space
0x10000-0x1007C
Reserved
0x10080
Maintenance
Interrupt
Maintenance module. These registers are described
in “Maintenance Interrupt Control Registers” on
page 6–34.
0x10084
Maintenance
Interrupt Enable
0x10088–0x100FC
Reserved
Table 6–4. Extended Features and Implementation-Defined Registers Memory Map (Part 2 of 3)
Address Name Used by Module
- User Guide 1
- RapidIO II MegaCore Function 1
- Contents 3
- Contents v 5
- Chapter 5. Signals 6
- Chapter 6. Software Interface 6
- Chapter 7. Testbench 6
- 1. About The RapidIO II 9
- MegaCore Function 9
- Releases 10
- RapidIO II IP Core Features 10
- Features 11
- Device Family Support 12
- IP Core Verification 13
- Hardware Testing 14
- Interoperability Testing 14
- Note to Table 1–3: 16
- Notes to Table 1–4: 16
- Installation and Licensing 17
- 2. Getting Started 19
- Simulating IP Cores 22
- Transceiver Settings 26
- External Transceiver PLL 26
- 3. Parameter Settings 31
- Note to Table 3–1: 32
- Enable 16-Bit Device ID Width 33
- Logical Layer Settings 34
- Capability Registers Settings 35
- Device ID 36
- Vendor ID 36
- Revision ID 36
- Assembly ID 36
- Assembly Information CAR 37
- Enable Flow Control Support 38
- Enable Switch Support 38
- Number of Ports 38
- Port Number 39
- Maximum PDU 39
- Destination Operations CAR 40
- Port General Control CSR 40
- Port 0 Control CSR 41
- Lane n Status 0 CSR 41
- Extended Features Pointer CSR 41
- 4. Functional Description 43
- Note to Table 4–2: 44
- Clocking and Reset Structure 45
- Notes to Table 4–3: 46
- RapidIO II 47
- Transactions 55
- Notes to Table 4–6: 57
- Notes to Table 4–7: 59
- Note to Table 4–8: 59
- Note to Figure 4–9: 66
- Note to Table 4–10: 70
- Notes to Table 4–11: 71
- Table 6–60 on page 6–40 72
- Note to Table 4–12: 73
- Maintenance Module 74
- Maintenance Interface Signals 75
- Doorbell Module Block Diagram 86
- Preserving Transaction Order 87
- Doorbell Module Signals 88
- Generating a Doorbell Message 88
- Receiving a Doorbell Message 89
- Transaction ID Ranges 90
- Notes to Table 4–24: 92
- Note to Table 4–26: 94
- Note to Table 4–27: 95
- field 97
- User Receiving Write Request 100
- Logical Layer Interfaces 101
- Transport Layer 112
- Receiver 113
- Transmitter 114
- Physical Layer 115
- Physical Layer Interfaces 116
- Low-level Interface Receiver 116
- CRC Checking and Removal 117
- Protocol Violations 119
- Fatal Errors 119
- Maintenance Avalon-MM Slave 120
- Maintenance Avalon-MM Master 121
- Port-Write Reception Module 122
- Input/Output Avalon-MM Slave 122
- Input/Output Avalon-MM Master 123
- 5. Signals 125
- Physical Layer Signals 126
- Low Latency Signals 127
- Multicast Event Signals 128
- Chapter 5: Signals 5–5 129
- Note to Table 5–7: 130
- Chapter 5: Signals 5–7 131
- 5–8 Chapter 5: Signals 132
- Register-Related Signals 133
- Avalon-MM Interface Signals 133
- Note to Table 5–12: 134
- Chapter 5: Signals 5–11 135
- Note to Table 5–15: 136
- Error Reporting Signals 137
- 5–14 Chapter 5: Signals 138
- 6. Software Interface 139
- Memory Map 140
- Physical Layer Registers 144
- Note to Table 6–9: 147
- Note to Table 6–14: 154
- Note to Table 6–15: 158
- Note to Table 6–17: 160
- Note to Table 6–22: 164
- Note to Table 6–23: 164
- Note to Table 6–24: 165
- Note to Table 6–25: 165
- Note to Table 6–26: 166
- Note to Table 6–27: 167
- Notes to Table 6–28: 168
- Notes to Table 6–29: 169
- Note to Table 6–30: 169
- Note to Table 6–31: 169
- Notes to Table 6–32: 170
- Note to Table 6–34: 171
- Note to Table 6–35: 171
- Note to Table 6–36: 172
- Note to Table 6–37: 172
- Transmit Port-Write Registers 174
- Receive Port-Write Registers 175
- Note to Table 6–59: 178
- Error Management Registers 180
- Note to Table 6–66: 181
- Notes to Table 6–67: 183
- Notes to Table 6–70: 185
- Notes to Table 6–71: 185
- Doorbell Message Registers 191
- Note to Table 6–89: 193
- 7. Testbench 195
- 7–2 Chapter 7: Testbench 196
- Testbench Overview 196
- Testbench Sequence 197
- 7–4 Chapter 7: Testbench 198
- Chapter 7: Testbench 7–5 199
- SWRITE Transactions 200
- NREAD Transactions 200
- NWRITE_R Transactions 201
- NWRITE Transactions 202
- Doorbell Transactions 202
- Port-Write Transactions 203
- Testbench Completion 204
- Chapter 7: Testbench 7–11 205
- 7–12 Chapter 7: Testbench 206
- A. Initialization Sequence 207
- MegaCore Function v12.1 209
- Additional Information 213
- Info–2 Additional Information 214
- Document Revision History 214
- Additional Information Info–3 215
- Info–4 Additional Information 216
- Note to Table: 217
- Info–6 Additional Information 218
- Typographic Conventions 218
Relacionado con productos y manuales para Instrumentos de medición Altera RapidIO II MegaCore Function
Instrumentos de medición Altera SerialLite III Streaming MegaCore Function Manual de usuario
(68 paginas)
(68 paginas)
Instrumentos de medición Altera Signal Integrity Development Kit, Stratix V GX Edi Manual de usuario
(52 paginas)
(52 paginas)
© 2020, manymanuals.es. Todos los derechos reservados | 0.018 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Comentarios a estos manuales