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Chapter 4: Functional Description 4–77
Error Detection and Management
August 2014 Altera Corporation RapidIO II MegaCore Function
User Guide
The RapidIO II IP core Physical layer transparently manages these errors for you. The
RapidIO specification defines both input and output error detection and recovery
state machines that include handshaking protocols in which the receiving end signals
that an error is detected by sending a
packet-not-accepted
control symbol, the
transmitter then sends an
input-status link-request
control symbol to which the
receiver responds with a
link-response
control symbol to indicate which packet
requires transmission. The input and output error detection and recovery state
machines can be monitored by software that you create to read the status of the
Port 0 Error and Status
CSR (Table 6–14 on page 6–12).
In addition to the registers defined by the specification, the RapidIO II IP core
provides several output signals that enable user logic to monitor error detection and
the recovery process. Refer to “Status Packet and Error Monitoring Signals” on
page 5–3.
Protocol Violations
Some protocol violations, such as a packet with an unexpected
ackID
or a time-out on
a packet acknowledgment, can use the same error recovery mechanisms as the
transmission errors described in “Physical Layer Error Management” on page 4–76.
Some protocol violations, such as a time-out on a link-request or the RapidIO II IP
core receiving a link-response with an
ackID
outside the range of transmitted
ackID
s,
can lead to unrecoverable—or fatal—errors.
Fatal Errors
Software determines the behavior of the RapidIO II IP core following a fatal error. For
example, you can program software to optionally perform any of the following
actions, among others:
■ Set the
PORT_DIS
bit of the
Port 0 Control
CSR (Table 6–15 on page 6–17) to force
the initialization state machine to the SILENT state.
■ Write to the
OUTBOUND_ACKID
field of the
Port 0 Local AckID
CSR (Table 6–12 on
page 6–10) to specify the next outbound and expected packet ackID from the
RapidIO link partner. You can use this option to force retransmission of
outstanding unacknowledged packets
■ Set the
CLR_OUTSTANDING_ACKIDS
field of the
Port 0 Local AckID
CSR (Table 6–12
on page 6–10) to clear the queue of outstanding unacknowledged packets.
If the link partner is reset when its expected
ackID
is not zero, a fatal error occurs
when the link partner receives the next transmitted packet because the link partner’s
expected
ackID
is reset to zero, which causes a mismatch between the transmitted
ackID
and the expected
ackID
. When that occurs, you can use the
Port 0 Local AckID
CSR to resynchronize the expected and transmitted
ackID
values.
Logical Layer Error Management
The Logical layer modules only need to process Logical layer errors because errors
detected by the Physical layer are masked from the Logical layer module. If an errored
packet arrives at the Transport layer, the Transport layer does not pass it on to the
Logical layer modules.
The RapidIO specification defines the following common errors and the protocols for
managing them:
- User Guide 1
- RapidIO II MegaCore Function 1
- Contents 3
- Contents v 5
- Chapter 5. Signals 6
- Chapter 6. Software Interface 6
- Chapter 7. Testbench 6
- 1. About The RapidIO II 9
- MegaCore Function 9
- Releases 10
- RapidIO II IP Core Features 10
- Features 11
- Device Family Support 12
- IP Core Verification 13
- Hardware Testing 14
- Interoperability Testing 14
- Note to Table 1–3: 16
- Notes to Table 1–4: 16
- Installation and Licensing 17
- 2. Getting Started 19
- Simulating IP Cores 22
- Transceiver Settings 26
- External Transceiver PLL 26
- 3. Parameter Settings 31
- Note to Table 3–1: 32
- Enable 16-Bit Device ID Width 33
- Logical Layer Settings 34
- Capability Registers Settings 35
- Device ID 36
- Vendor ID 36
- Revision ID 36
- Assembly ID 36
- Assembly Information CAR 37
- Enable Flow Control Support 38
- Enable Switch Support 38
- Number of Ports 38
- Port Number 39
- Maximum PDU 39
- Destination Operations CAR 40
- Port General Control CSR 40
- Port 0 Control CSR 41
- Lane n Status 0 CSR 41
- Extended Features Pointer CSR 41
- 4. Functional Description 43
- Note to Table 4–2: 44
- Clocking and Reset Structure 45
- Notes to Table 4–3: 46
- RapidIO II 47
- Transactions 55
- Notes to Table 4–6: 57
- Notes to Table 4–7: 59
- Note to Table 4–8: 59
- Note to Figure 4–9: 66
- Note to Table 4–10: 70
- Notes to Table 4–11: 71
- Table 6–60 on page 6–40 72
- Note to Table 4–12: 73
- Maintenance Module 74
- Maintenance Interface Signals 75
- Doorbell Module Block Diagram 86
- Preserving Transaction Order 87
- Doorbell Module Signals 88
- Generating a Doorbell Message 88
- Receiving a Doorbell Message 89
- Transaction ID Ranges 90
- Notes to Table 4–24: 92
- Note to Table 4–26: 94
- Note to Table 4–27: 95
- field 97
- User Receiving Write Request 100
- Logical Layer Interfaces 101
- Transport Layer 112
- Receiver 113
- Transmitter 114
- Physical Layer 115
- Physical Layer Interfaces 116
- Low-level Interface Receiver 116
- CRC Checking and Removal 117
- Protocol Violations 119
- Fatal Errors 119
- Maintenance Avalon-MM Slave 120
- Maintenance Avalon-MM Master 121
- Port-Write Reception Module 122
- Input/Output Avalon-MM Slave 122
- Input/Output Avalon-MM Master 123
- 5. Signals 125
- Physical Layer Signals 126
- Low Latency Signals 127
- Multicast Event Signals 128
- Chapter 5: Signals 5–5 129
- Note to Table 5–7: 130
- Chapter 5: Signals 5–7 131
- 5–8 Chapter 5: Signals 132
- Register-Related Signals 133
- Avalon-MM Interface Signals 133
- Note to Table 5–12: 134
- Chapter 5: Signals 5–11 135
- Note to Table 5–15: 136
- Error Reporting Signals 137
- 5–14 Chapter 5: Signals 138
- 6. Software Interface 139
- Memory Map 140
- Physical Layer Registers 144
- Note to Table 6–9: 147
- Note to Table 6–14: 154
- Note to Table 6–15: 158
- Note to Table 6–17: 160
- Note to Table 6–22: 164
- Note to Table 6–23: 164
- Note to Table 6–24: 165
- Note to Table 6–25: 165
- Note to Table 6–26: 166
- Note to Table 6–27: 167
- Notes to Table 6–28: 168
- Notes to Table 6–29: 169
- Note to Table 6–30: 169
- Note to Table 6–31: 169
- Notes to Table 6–32: 170
- Note to Table 6–34: 171
- Note to Table 6–35: 171
- Note to Table 6–36: 172
- Note to Table 6–37: 172
- Transmit Port-Write Registers 174
- Receive Port-Write Registers 175
- Note to Table 6–59: 178
- Error Management Registers 180
- Note to Table 6–66: 181
- Notes to Table 6–67: 183
- Notes to Table 6–70: 185
- Notes to Table 6–71: 185
- Doorbell Message Registers 191
- Note to Table 6–89: 193
- 7. Testbench 195
- 7–2 Chapter 7: Testbench 196
- Testbench Overview 196
- Testbench Sequence 197
- 7–4 Chapter 7: Testbench 198
- Chapter 7: Testbench 7–5 199
- SWRITE Transactions 200
- NREAD Transactions 200
- NWRITE_R Transactions 201
- NWRITE Transactions 202
- Doorbell Transactions 202
- Port-Write Transactions 203
- Testbench Completion 204
- Chapter 7: Testbench 7–11 205
- 7–12 Chapter 7: Testbench 206
- A. Initialization Sequence 207
- MegaCore Function v12.1 209
- Additional Information 213
- Info–2 Additional Information 214
- Document Revision History 214
- Additional Information Info–3 215
- Info–4 Additional Information 216
- Note to Table: 217
- Info–6 Additional Information 218
- Typographic Conventions 218
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