Altera Viterbi Compiler Manual de usuario

Viterbi IP Core User GuideSubscribeSend FeedbackUG-VITERBI2014.12.15101 Innovation DriveSan Jose, CA 95134www.altera.com

Viterbi IP Core Getting Started22014.12.15UG-VITERBISubscribeSend Feedback1.Installing and Licensing IP CoresThe Altera IP Library provides many usefu

• Simulate the behavior of a licensed IP core in your system.• Verify the functionality, size, and speed of the IP core quickly and easily.• Generate

Figure 2-2: Quartus II IP CatalogSearch for installed IP coresDouble-click to customize, right-click for detailed informationShow IP only for target d

• Optionally select preset parameter values if provided for your IP core. Presets specify initialparameter values for specific applications.• Specify

Figure 2-4: IP Core Generated Files<your_testbench>_tb.csv<your_testbench>_tb.spd<your_ip>.cmp - VHDL component declaration file<

File Name Description<my_ip>.cmp The VHDL Component Declaration (.cmp) file is a text file thatcontains local generic and port definitions that

File Name Description<my_ip>.svdAllows HPS System Debug tools to view the register maps ofperipherals connected to HPS within a Qsys system.Duri

Figure 2-5: Simulation in Quartus II Design FlowPost-fit timing simulation netlist Post-fit timing simulation (3)Post-fit functional simulation net

Related InformationUsing MegaCore Functions chapter in the DSP Builder Handbook.UG-VITERBI2014.12.15DSP Builder Design Flow2-9Viterbi IP Core Getting

Viterbi IP Core Functional Description32014.12.15UG-VITERBISubscribeSend FeedbackDecoderThe Viterbi decoder can be a continuous or block decoder.The c

ContentsAbout the Viterbi IP Core...1-1Altera DSP IP Core Features...

Trellis Coded ModulationTrellis coded modulation (TCM) combines modulation and encoding processes to achieve betterefficiency without increasing the b

Figure 3-3: Mapping of Coded Bits and Sector NumbersThe specific mapping is not important. You can derive other mappings by permutating subsets in a w

Figure 3-4: Four-State TrellisThe four-state trellis is the trellis for the 1/2 rate convolution encoder with the addition of parallel paths ineach tr

Figure 3-5: Implementation of the Viterbi Decoder as a Trellis Decoderdecdat0ViterbiDecoderTrellis ModeRate 1/2ConvolutionalEncoderTrellisOutput Demap

Figure 3-6: Conversion of Received Symbol into Four Branch Metrics and a Sector NumberBranch Metric 1Branch Metric 3Branch Metric 2Branch Metric 0Rece

Trellis TerminationBlock decoders must properly decode the last bits of the block and adapt to the convolutional encoder.Tail-biting feeds the convolu

Parameter Value DescriptionBER On or Off Specifies the BER estimatoroption, refer to “BER Estimator”on page 3–7.Node Sync On or Off Specifies the node

Figure 3-8: Graph Comparing Actual BER with Estimated BER3.00 3.50 4.00 4.50 5.005.50 6.00Signal-to-Noise RatioBERActual BEREstimated BER1.00e-031.00e

Table 3-2: Code Sets ParametersParameter Value DescriptionNumber ofCode Sets1 to 8 The Viterbi IP core supports multiple code definitions. The multipl

Parameter Value DescriptionACS Units (A) 1, 2, 4, 8, or 16 The number of ACS units, whichadds a degree of parallelism(hybrid architecture only). Thera

Document Revision History...4-1TOC-3Altera Corporation

Soft Symbol Meaning100 Strongest '1'State MetricsThe Viterbi decoder state metrics are accumulative not Euclidean and are based on maximum m

Parameter DescriptionNumber of bits per blockThe number of bits per block.The number of bits per block × the number of blocks must be less than50,000,

Viterbi IP Core Interfaces and SignalsThe Viterbi Avalon-ST interface supports backpressure, which is a flow control mechanism, where a sinkcan indica

Signal NameAvalon-STNameDirection Descriptioneras_sym[Nmax:1]dat Input When asserted, eras_sym Indicates an erased symbol. Bothrr and eras_sym are Ava

Signal NameAvalon-STNameDirection Descriptionsink_data data InputIn Qsys systems, this Avalon-ST-compliant data busincludes all the Avalon-ST input da

SignalAvalon-STNameDirection Descriptionout_data data OutputIn Qsys systems, this Avalon-ST-compliant data busincludes all the Avalon-ST output data a

Signal Name Descriptiontb_type Altera recommends that you set tb_type high always for futurecompatibility. In block decoding when tb_type is low, the

Figure 3-10: Hybrid Decoder Input Timing DiagramThe sink_rdy signal is asserted for one clock cycle in every Z clock cycles. If the decoder becomes fu

Figure 3-13: Output Timing - Example 2With a different ending.clksource_sopsource_eopsource_rdysource_valdecbitFigure 3-14: Depuncturing Timing Diagra

Document Revision History42014.12.15UG-VITERBISubscribeSend FeedbackViterbi IP Core User Guide revision history.Date Version Changes Made2014.12.15 14

About the Viterbi IP Core12014.12.15UG-VITERBISubscribeSend FeedbackAltera DSP IP Core Features• Avalon® Streaming (Avalon-ST) interfaces• DSP Builder

Date Version Changes MadeMay 2011 11.0• Updated support level to final support for ArriaII GX, Arria II GZ, Cyclone III LS, and CycloneIV GX devices.•

DSP IP Core Device Family SupportAltera® offers the following device support levels for Altera IP cores:• Preliminary support—Altera verifies the IP c

Item DescriptionRelease Date December 2014Ordering Code IP-VITERBI/HS (parallel architecture) IP-VITERBI/SS (hybridarchitecture)Product ID 0037 (paral

ParametersDevice ALM fMAX (MHz)Memory RegistersL A M10K M20K Primary Secondary7 1 Arria V 427 207 6 -- 507 587 1 Cyclone V 427 185 6 -- 507 747 1 Stra

Parallel ArchitectureThe typical expected performance for a parallel Viterbi IP core uses the Quartus II software with the ArriaV (5AGXFB3H4F40C4), Cy

ParametersDevice ALMsfMAX(MHz)Memory Registerssoftbits L OptimizationBestStateFinderM10K M20K Primary Secondary5 3 — On CycloneV397 188 5 -- 484 815 3