Altera SerialLite II IP Core Manual de usuario Pagina 96
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5–10 Chapter 5: Testbench
Testbench Components Description
SerialLite II MegaCore Function January 2014 Altera Corporation
User Guide
The first byte of each generated packet is a sequential identifier (id) that seeds the
LFSR. Every time the
send_packet
task is called, the agen id is incremented by one.
The module operates in one of two modes: data port or priority port. When in priority
port mode, the Atlantic
dav
signal is ignored for all but the first transfer of a packet.
There can be multiple agen instantiations (for data and priority port, DUT and
SISTER), depending on the DUT’s chosen parameters.
AGEN Tasks
This sections defines the AGEN tasks.
–
send_packet(addr,size[31:0],err)
send_packet
is the main AGEN task. It causes a packet of a specified size and
destined for a particular address to be transmitted. The
err
bit may also be assigned a
value. The data is based on a LFSR.
Figure 5–1 describes the
send_packet
task fields.
–
ipg(min[31:0],max[31:0])
If the
gap
task is called, successive packets are separated by a a random number of
idle cycles.
–
gap(prob[31:0],min[31:0],max[31:0])
Table 5–1. send_packet Task Field Description
Field Location
in Task
Field Valid Values Description
1
addr
0 to 0xFF (data)
0 to 0xF (priority)
Set to 0.
2
size
0 to 0xFFFF_FFFF (bytes)
The
size
field sets the size, in bytes, of the current packet
being sent by this task.
3
err
1'b0 or 1'b1
The
err
field determines whether an Atlantic error is
asserted at the end of a packet when
eop
is asserted. You
can optionally set it to 1'b1 to set the error flag for that
packet.
Table 5–2. gap Task Field Description
Field Location
in Task
Field Valid Values Description
1
min
0 to 0xFFFF_FFFF
(cycles)
The
min
field sets the minimum value, in Atlantic clock
cycles, for a random gap between two packets.
2
max
0 to 0xFFFF_FFFF
(cycles)
The
max
field sets the maximum value, in Atlantic clock
cycles, for a random gap between two packets.
A
max
field greater than or equal to the
min
field is required.
When
max==min
, no gap occurs.
- User Guide 1
- Contents 3
- Chapter 5. Testbench 5
- Release Information 6
- Device Family Support 6
- Features 7
- General Description 8
- (EP2GX90FF1508C3) 10
- Notes to Table 1–3: 11
- Installation and Licensing 13
- OpenCore Plus Evaluation 14
- Simulate with Testbench 16
- Design Flow 17
- Parameterize 18
- Set Up Simulation 21
- Generate Files 21
- Simulate the Design 22
- Instantiate the MegaCore 22
- Specify Constraints 22
- Compile and Program 23
- 3. Parameter Settings 24
- Link Consistency 25
- Physical Layer Configuration 25
- Transfer size 26
- Reference Clock Frequency 26
- Port Type 27
- Notes to Figure 3–3: 28
- Note to Figure 3–4: 28
- Note to Figure 3–5: 29
- Notes to Figure 3–6: 29
- Self Synchronized Link Up 30
- Number of Lanes 31
- Scramble 32
- De-Scramble 32
- Broadcast Mode 32
- Clock Compensation 33
- Link Layer Configuration 34
- Retry-on-error Disabled 35
- Retry-on-error Enabled 35
- Segment Size 35
- Retry-on-error 36
- Retry-on-error Responses 37
- Flow Control 38
- Notes to Figure 3–12: 41
- Notes to Table 3–6: 42
- Transmit/Receive FIFO Buffers 43
- FIFO Buffer Size 44
- FIFO Buffer Structure 44
- 16-Bit Versus 32-Bit CRC 46
- Transceiver Configuration 47
- Transmitter Buffer Power (V 48
- Equalizer Control Settings 48
- Bandwidth Mode 48
- Starting Channel number 49
- ALTGX Support Signals 50
- Error Handling 51
- Optimizing the Implementation 52
- Feature Selection 53
- Running Different Seeds 53
- Limiting Fanout 53
- Floorplanning 53
- Minimizing Memory Utilization 54
- 4. Functional Description 55
- Atlantic Interface 56
- High-Speed Serial Interface 57
- Clocks and Data Rates 58
- External Clock Modes 59
- SerialLite II Deskew Support 60
- Note to Figure 4–6: 61
- Note to Figure 4–7: 62
- Note to Figure 4–8: 63
- Note to Figure 4–9: 64
- Note to Figure 4–10: 65
- Note to Figure 4–11: 66
- Note to Figure 4–14: 69
- Initialization and Restart 71
- Multiple Core Configuration 72
- Compilation 73
- Testbench 74
- Simulation Support 74
- Notes to Table 4–5: 77
- Notes to Table 4–6: 79
- Notes to Table 4–7: 81
- Notes to Table 4–8: 81
- Notes to Table 4–9: 82
- Note to Table 4–10: 84
- MegaCore Verification 85
- 5. Testbench 87
- Testbench Specifications 88
- Notes to Figure 5–1: 89
- 5–4 Chapter 5: Testbench 90
- Simulation Flow 91
- Running a Simulation 92
- Chapter 5: Testbench 5–7 93
- Testbench Time-Out 94
- Verilog HDL 95
- 5–10 Chapter 5: Testbench 96
- Chapter 5: Testbench 5–11 97
- Chapter 5: Testbench 5–13 99
- 5–14 Chapter 5: Testbench 100
- Status Monitors (pin_mon) 101
- Pin_mon Tasks - Verilog HDL 102
- Chapter 5: Testbench 5–17 103
- 5–18 Chapter 5: Testbench 104
- Chapter 5: Testbench 5–19 105
- 5–20 Chapter 5: Testbench 106
- Chapter 5: Testbench 5–21 107
- Additional Information 108
- Typographic Conventions 109
- Visual Cue Meaning 110
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