Altera SerialLite II IP Core Manual de usuario descargar pdf (Pagina 45)

3–22 Chapter 3: Parameter Settings

Link Layer Configuration

SerialLite II MegaCore Function January 2014 Altera Corporation

User Guide

The receiver Atlantic FIFO buffers include an end-of-packet based data available

feature which can be turned on by asserting the

ctl_rxrdp_eopdav/ctl_rxhpp_eopdav

signals. The end-of-packet feature determines whether the

dav

remains high: if the

signal is asserted, and there is an end-of- packet beneath the FTL threshed, the

dav

signal remains high until the end-of-packet is read out of the FIFO buffer. Otherwise,

if the signal is not asserted, the

dav

signal only remains high when the fill level of the

buffer is higher than the FTL value.

ctl_rxhpp_fth

and

ctl_rxrdp_fth

are the threshold levels for the high priority and

regular data ports on the receiver Atlantic FIFO buffers. When the data fill level is

higher than the threshold level set by

ctl_rxhpp_fth

ctl_rxrdp_fth

dav

=1, it

means that there a large amount of data ready to be fetched at the FIFO buffer. You

must set these threshold levels based on your design requirements, and ensure that

the FIFO buffer does not underflow. You may also set the threshold levels to segment

size of a priority packet; or to the lowest level so that you can fetch data as soon as it is

stored in the FIFO buffer.

You can set

ctl_rxhpp_ftl

to 1 element unit so that it fetches the data from the RX

FIFO buffer as soon as there is data available. If you want to store some data before

fetching it, you can raise the threshold level.

The FIFO buffer threshold high (

ctl_txrdp_fth/ctl_txhpp_fth

) value for transmitter

variations controls when the

txrdp_dav/txhpp_dav

signals are asserted and

deasserted for the write side of the FIFO buffer, respectively. The

txrdp_dav

signal

indicates when there is room available to write new data into the FIFO buffer, and is

asserted when the fill level of the FIFO is less than the FTH setting, and deasserted

when the fill level of the FIFO is greater than the FTH.

For example, if FTH is five, and the fill level is four, the

txrdp_dav/txhpp_dav

signal is

high, indicating that the user can write data into the FIFO. If the fill level for this

example is six, the

txrdp_dav/txhpp_dav

signal is low, indicating that the user should

stop writing data into the FIFO.

ctl_txhpp_fth

and

ctl_txrdp_fth

are the threshold levels for the high priority and

regular data ports on the transmitter Atlantic FIFO buffers. When the data fill level at

the FIFO buffer is lower than the threshold level set by

ctl_txhpp_fth

ctl_txrdp_fth

, or

dav

= 1, it means that there are plenty of spaces available for data to

write into the buffer. You must set these threshold levels high so that the user logic

knows whenever the FIFO buffer has available spaces for data buffering and to ensure

that overflow does not occur. However, these threshold settings should not exceed the

FIFO depth.

For example, if the transmitter buffer size is 4,096 bytes, and the transmitter FIFO

depth is 2,048 element units, you should set the level of

ctl_txhpp_fth

to 250 element

units.

TSIZE

= 2, and one FIFO element = 2 bytes

Maximum TX FIFO level (TX 8 lane) = 2,048/8 = 256 element units

1 You can set any value below 256 element units for

ctl_txhpp_fth

; Altera

recommends a level of 250 element units or 8'hFA.

1 2 ... 40 41 42 43 44 45 46 47 48 49 50 ... 109 110

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Altera SerialLite II IP Core Manual de usuario Pagina 45

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