Altera SerialLite II IP Core Manual de usuario Pagina 80
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Valorado. / 5. Basado en revisión del cliente
4–26 Chapter 4: Functional Description
Signals
SerialLite II MegaCore Function January 2014 Altera Corporation
User Guide
rxrdp_eop
(1)
Output
rxrdp_clk
End of packet indicator on the Atlantic interface.
rxrdp_err
(1)
Output
rxrdp_clk
Error indicator on the Atlantic Interface. This signal is
not necessarily held high until
rxrdp_eop
is
asserted.
rxrdp_mty[
m
-1:0]
(1)
,
(2)
Output
rxrdp_clk
Number of empty bytes in the data word.
rxrdp_dat[
d
-1:0]
(1)
,
(3)
Output
rxrdp_clk
User data bits.
rxrdp_adr[7:0]
(1)
Output
rxrdp_clk
User-defined packet ID. Only valid with
rxrdp_sop
.
txrdp_ena
Input
txrdp_clk
Enable signal on the Atlantic interface. Indicates that
the data is valid.
txrdp_dav
Output
txrdp_clk
Indicates that the input FIFO buffer is not full.
txrdp_sop
Input
txrdp_clk
Start of packet indicator on the Atlantic interface.
txrdp_eop
Input
txrdp_clk
End of packet indicator on the Atlantic interface.
txrdp_err
Input
txrdp_clk
Error indicator on the Atlantic interface.
txrdp_mty[
tm
-1:0]
(4)
Input
txrdp_clk
Number of empty bytes in the data word.
txrdp_dat[
td
-1:0]
(5)
Input
txrdp_clk
User data bits.
txrdp_adr[7:0]
Input
txrdp_clk
User-defined packet ID.
rxhpp_ena
(1)
Input
rxhpp_clk
Enable signal on the Atlantic interface. Indicates that
the data is to be read on the next clock cycle.
rxhpp_dav
(1)
Input
rxhpp_clk
Input (No FIFO buffer) determines whether flow
control is required on this port.When this signal is
low, the fill level has been breached. When this signal
is high, the FIFO buffer has enough space for more
words.
rxhpp_dav
(1)
Output
rxhpp_clk
Output (With FIFO buffer) represents the buffer’s fill
level. This signal is high when the level is above FTL
or if an EOP is in the buffer.
rxhpp_val
(1)
Output
rxhpp_clk
The output data is valid.
rxhpp_sop
(1)
Output
rxhpp_clk
Start of packet indicator on the Atlantic interface.
rxhpp_eop
(1)
Output
rxhpp_clk
End of packet indicator on the Atlantic interface.
rxhpp_err
(1)
Output
rxhpp_clk
Error indicator on the Atlantic Interface. This signal is
not necessarily held high until
rxhpp_eop
is
asserted.
rxhpp_mty[
m
-1:0]
(1)
,
(2)
Output
rxhpp_clk
Number of empty bytes in the data word.
rxhpp_dat[
d
-1:0]
(1)
,
(3)
Output
rxhpp_clk
User data bits.
rxhpp_adr[3:0]
(1)
Output
rxhpp_clk
User-defined packet ID. Only valid with
rxhpp_sop
.
txhpp_ena
Input
txhpp_clk
Enable signal on the Atlantic interface. Indicates that
the data is valid.
txhpp_dav
Output
txhpp_clk
Indicates that the input FIFO buffer is not full.
txhpp_sop
Input
txhpp_clk
Start of packet indicator on the Atlantic interface.
txhpp_eop
Input
txhpp_clk
End of packet indicator on the Atlantic interface.
Table 4–7. Atlantic Interface Signals (Part 2 of 3)
Signal Direction Clock Domain Description
- User Guide 1
- Contents 3
- Chapter 5. Testbench 5
- Release Information 6
- Device Family Support 6
- Features 7
- General Description 8
- (EP2GX90FF1508C3) 10
- Notes to Table 1–3: 11
- Installation and Licensing 13
- OpenCore Plus Evaluation 14
- Simulate with Testbench 16
- Design Flow 17
- Parameterize 18
- Set Up Simulation 21
- Generate Files 21
- Simulate the Design 22
- Instantiate the MegaCore 22
- Specify Constraints 22
- Compile and Program 23
- 3. Parameter Settings 24
- Link Consistency 25
- Physical Layer Configuration 25
- Transfer size 26
- Reference Clock Frequency 26
- Port Type 27
- Notes to Figure 3–3: 28
- Note to Figure 3–4: 28
- Note to Figure 3–5: 29
- Notes to Figure 3–6: 29
- Self Synchronized Link Up 30
- Number of Lanes 31
- Scramble 32
- De-Scramble 32
- Broadcast Mode 32
- Clock Compensation 33
- Link Layer Configuration 34
- Retry-on-error Disabled 35
- Retry-on-error Enabled 35
- Segment Size 35
- Retry-on-error 36
- Retry-on-error Responses 37
- Flow Control 38
- Notes to Figure 3–12: 41
- Notes to Table 3–6: 42
- Transmit/Receive FIFO Buffers 43
- FIFO Buffer Size 44
- FIFO Buffer Structure 44
- 16-Bit Versus 32-Bit CRC 46
- Transceiver Configuration 47
- Transmitter Buffer Power (V 48
- Equalizer Control Settings 48
- Bandwidth Mode 48
- Starting Channel number 49
- ALTGX Support Signals 50
- Error Handling 51
- Optimizing the Implementation 52
- Feature Selection 53
- Running Different Seeds 53
- Limiting Fanout 53
- Floorplanning 53
- Minimizing Memory Utilization 54
- 4. Functional Description 55
- Atlantic Interface 56
- High-Speed Serial Interface 57
- Clocks and Data Rates 58
- External Clock Modes 59
- SerialLite II Deskew Support 60
- Note to Figure 4–6: 61
- Note to Figure 4–7: 62
- Note to Figure 4–8: 63
- Note to Figure 4–9: 64
- Note to Figure 4–10: 65
- Note to Figure 4–11: 66
- Note to Figure 4–14: 69
- Initialization and Restart 71
- Multiple Core Configuration 72
- Compilation 73
- Testbench 74
- Simulation Support 74
- Notes to Table 4–5: 77
- Notes to Table 4–6: 79
- Notes to Table 4–7: 81
- Notes to Table 4–8: 81
- Notes to Table 4–9: 82
- Note to Table 4–10: 84
- MegaCore Verification 85
- 5. Testbench 87
- Testbench Specifications 88
- Notes to Figure 5–1: 89
- 5–4 Chapter 5: Testbench 90
- Simulation Flow 91
- Running a Simulation 92
- Chapter 5: Testbench 5–7 93
- Testbench Time-Out 94
- Verilog HDL 95
- 5–10 Chapter 5: Testbench 96
- Chapter 5: Testbench 5–11 97
- Chapter 5: Testbench 5–13 99
- 5–14 Chapter 5: Testbench 100
- Status Monitors (pin_mon) 101
- Pin_mon Tasks - Verilog HDL 102
- Chapter 5: Testbench 5–17 103
- 5–18 Chapter 5: Testbench 104
- Chapter 5: Testbench 5–19 105
- 5–20 Chapter 5: Testbench 106
- Chapter 5: Testbench 5–21 107
- Additional Information 108
- Typographic Conventions 109
- Visual Cue Meaning 110
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