Altera SerialLite II IP Core Manual de usuario Pagina 70
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Valorado. / 5. Basado en revisión del cliente
4–16 Chapter 4: Functional Description
Clocks and Data Rates
SerialLite II MegaCore Function January 2014 Altera Corporation
User Guide
Figure 4–15. Receiver Link Layer With FIFO
slite2_top
high speed front
end (Phy)
slite2_ll
RX Core
Regular Data
Port Atlantic
FIFO
(rxrdp_atltop)
rxrdp_ena
rxrdp_dav
rxrdp_sop
rxrdp_eop
rxrdp_err
rxrdp_mty
rxrdp_dat
rxrdp_adr
Atlantic
Interface
(Reg Data
Packets )
rxrdp_clk
ctrl_rr_rdp_fcthresh
Phy Layer
Blocks (Ex
xcvr,
slite2_phy)
rxrdp_val
High Priority
Port Atlantic
FIFO
(rxhpp_atltop)
rxhpp_ena
rxhpp_dav
rxhpp_sop
rxhpp_eop
rxhpp_err
rxhpp_mty
rxhpp_dat
rxhpp_adr
Atlantic
Interface
(Priority
Packets )
rxhpp_clk
ctrl_rr_hpp_fcthresh
stat_rxhpp_empty
rxhpp_val
rrefclk
tx_coreclock
ctl_rxhpp_ftl
ctl_rxhpp_eopdav
stat_rxrdp_empty
ctl_rxrdp_ftl
ctl_rxrdp_eopdav
err_tc/rr_rxrdp_ofl
w
err_tc/rr_rxhpp_ofl
w
err_rr_foffre_oflw
stat_tc_foffre_empty
stat_rr_ebprx
err_rr_bip8
err_rr_crc
err_rr_in
v
alid_lmprx
err_rr_missing_start_dcw
err_rr_addr_mismatch
err_rr_rx2txfifo_oflw
stat_rr_fc_rdp_
valid
stat_rr_fc_hpp_
valid
stat_rr_fc_
value
stat_rr_roe_ack
stat_rr_roe_nack
rx2tx_retimer_fifo
To TX Core
- User Guide 1
- Contents 3
- Chapter 5. Testbench 5
- Release Information 6
- Device Family Support 6
- Features 7
- General Description 8
- (EP2GX90FF1508C3) 10
- Notes to Table 1–3: 11
- Installation and Licensing 13
- OpenCore Plus Evaluation 14
- Simulate with Testbench 16
- Design Flow 17
- Parameterize 18
- Set Up Simulation 21
- Generate Files 21
- Simulate the Design 22
- Instantiate the MegaCore 22
- Specify Constraints 22
- Compile and Program 23
- 3. Parameter Settings 24
- Link Consistency 25
- Physical Layer Configuration 25
- Transfer size 26
- Reference Clock Frequency 26
- Port Type 27
- Notes to Figure 3–3: 28
- Note to Figure 3–4: 28
- Note to Figure 3–5: 29
- Notes to Figure 3–6: 29
- Self Synchronized Link Up 30
- Number of Lanes 31
- Scramble 32
- De-Scramble 32
- Broadcast Mode 32
- Clock Compensation 33
- Link Layer Configuration 34
- Retry-on-error Disabled 35
- Retry-on-error Enabled 35
- Segment Size 35
- Retry-on-error 36
- Retry-on-error Responses 37
- Flow Control 38
- Notes to Figure 3–12: 41
- Notes to Table 3–6: 42
- Transmit/Receive FIFO Buffers 43
- FIFO Buffer Size 44
- FIFO Buffer Structure 44
- 16-Bit Versus 32-Bit CRC 46
- Transceiver Configuration 47
- Transmitter Buffer Power (V 48
- Equalizer Control Settings 48
- Bandwidth Mode 48
- Starting Channel number 49
- ALTGX Support Signals 50
- Error Handling 51
- Optimizing the Implementation 52
- Feature Selection 53
- Running Different Seeds 53
- Limiting Fanout 53
- Floorplanning 53
- Minimizing Memory Utilization 54
- 4. Functional Description 55
- Atlantic Interface 56
- High-Speed Serial Interface 57
- Clocks and Data Rates 58
- External Clock Modes 59
- SerialLite II Deskew Support 60
- Note to Figure 4–6: 61
- Note to Figure 4–7: 62
- Note to Figure 4–8: 63
- Note to Figure 4–9: 64
- Note to Figure 4–10: 65
- Note to Figure 4–11: 66
- Note to Figure 4–14: 69
- Initialization and Restart 71
- Multiple Core Configuration 72
- Compilation 73
- Testbench 74
- Simulation Support 74
- Notes to Table 4–5: 77
- Notes to Table 4–6: 79
- Notes to Table 4–7: 81
- Notes to Table 4–8: 81
- Notes to Table 4–9: 82
- Note to Table 4–10: 84
- MegaCore Verification 85
- 5. Testbench 87
- Testbench Specifications 88
- Notes to Figure 5–1: 89
- 5–4 Chapter 5: Testbench 90
- Simulation Flow 91
- Running a Simulation 92
- Chapter 5: Testbench 5–7 93
- Testbench Time-Out 94
- Verilog HDL 95
- 5–10 Chapter 5: Testbench 96
- Chapter 5: Testbench 5–11 97
- Chapter 5: Testbench 5–13 99
- 5–14 Chapter 5: Testbench 100
- Status Monitors (pin_mon) 101
- Pin_mon Tasks - Verilog HDL 102
- Chapter 5: Testbench 5–17 103
- 5–18 Chapter 5: Testbench 104
- Chapter 5: Testbench 5–19 105
- 5–20 Chapter 5: Testbench 106
- Chapter 5: Testbench 5–21 107
- Additional Information 108
- Typographic Conventions 109
- Visual Cue Meaning 110
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