Altera SerialLite II IP Core Manual de usuario Pagina 101
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Valorado. / 5. Basado en revisión del cliente
Chapter 5: Testbench 5–15
Testbench Components Description
January 2014 Altera Corporation SerialLite II MegaCore Function
User Guide
– PRIORITY
A value of one causes the model to receive data intended for a priority port, so that
Atlantic
dav
signal is ignored for all but the first transfer of a packet. A value of zero
causes the model to receive data intended for a data port, so
dav
is always obeyed.
defparam amon_dat_dut.PRIORITY=0;
defparam amon_pri_dut.PRIORITY=1;
– PORT_NAME
A string used to distinguish between verbose messages coming from multiple
instances of AMON.
defparam amon_dat_dut.PORT_NAME = "AMON_DAT_DUT";
defparam amon_pri_sis.PORT_NAME = "AMON_PRI_SIS";
VHDL
The VHDL version of the
AMON
module monitors the Atlantic data received (instances:
amon_dat_dut
,
amon_dat_sis
). The data received is based on a incrementing pattern.
The AMON monitor performs the following functions:
■ Validates transmission of individual packets by extracting the intended packet size
from the SOP and checking it against the actual value of the packet size counter in
the EOP.
■ Counts the total number of packets (provided as an output) to ensure that the all
packets sent are also received.
■ Checks Atlantic packets for missing SOP and EOP signals.
If any errors are detected by the
AMON
monitor, the
error_detect
output signal is
asserted.
Inner packet read gaps can optionally be enabled by driving the
ipg
input to the
module with a one. Doing so changes the behavior of the Atlantic read enable so that
it is instead controlled by the output of a pseudo random generator. Verbose mode for
the utility is enabled by setting the
verbose
integer in the generic map to one.
Status Monitors (pin_mon)
The simulation includes status pin monitors for the DUT and SISTERs
(
pin_mon_
<pin_name>). When enabled (by default), the status monitor compares the
received data against the expected data. If the expected value is different from the
current value, the monitor flags an error.
Set the
en
input pin high to enable a pin monitor, low to disable a pin monitor, or for
Verilog HDL only use the tasks. The Verilog HDL pin monitor expected value can be
set by a task.
- User Guide 1
- Contents 3
- Chapter 5. Testbench 5
- Release Information 6
- Device Family Support 6
- Features 7
- General Description 8
- (EP2GX90FF1508C3) 10
- Notes to Table 1–3: 11
- Installation and Licensing 13
- OpenCore Plus Evaluation 14
- Simulate with Testbench 16
- Design Flow 17
- Parameterize 18
- Set Up Simulation 21
- Generate Files 21
- Simulate the Design 22
- Instantiate the MegaCore 22
- Specify Constraints 22
- Compile and Program 23
- 3. Parameter Settings 24
- Link Consistency 25
- Physical Layer Configuration 25
- Transfer size 26
- Reference Clock Frequency 26
- Port Type 27
- Notes to Figure 3–3: 28
- Note to Figure 3–4: 28
- Note to Figure 3–5: 29
- Notes to Figure 3–6: 29
- Self Synchronized Link Up 30
- Number of Lanes 31
- Scramble 32
- De-Scramble 32
- Broadcast Mode 32
- Clock Compensation 33
- Link Layer Configuration 34
- Retry-on-error Disabled 35
- Retry-on-error Enabled 35
- Segment Size 35
- Retry-on-error 36
- Retry-on-error Responses 37
- Flow Control 38
- Notes to Figure 3–12: 41
- Notes to Table 3–6: 42
- Transmit/Receive FIFO Buffers 43
- FIFO Buffer Size 44
- FIFO Buffer Structure 44
- 16-Bit Versus 32-Bit CRC 46
- Transceiver Configuration 47
- Transmitter Buffer Power (V 48
- Equalizer Control Settings 48
- Bandwidth Mode 48
- Starting Channel number 49
- ALTGX Support Signals 50
- Error Handling 51
- Optimizing the Implementation 52
- Feature Selection 53
- Running Different Seeds 53
- Limiting Fanout 53
- Floorplanning 53
- Minimizing Memory Utilization 54
- 4. Functional Description 55
- Atlantic Interface 56
- High-Speed Serial Interface 57
- Clocks and Data Rates 58
- External Clock Modes 59
- SerialLite II Deskew Support 60
- Note to Figure 4–6: 61
- Note to Figure 4–7: 62
- Note to Figure 4–8: 63
- Note to Figure 4–9: 64
- Note to Figure 4–10: 65
- Note to Figure 4–11: 66
- Note to Figure 4–14: 69
- Initialization and Restart 71
- Multiple Core Configuration 72
- Compilation 73
- Testbench 74
- Simulation Support 74
- Notes to Table 4–5: 77
- Notes to Table 4–6: 79
- Notes to Table 4–7: 81
- Notes to Table 4–8: 81
- Notes to Table 4–9: 82
- Note to Table 4–10: 84
- MegaCore Verification 85
- 5. Testbench 87
- Testbench Specifications 88
- Notes to Figure 5–1: 89
- 5–4 Chapter 5: Testbench 90
- Simulation Flow 91
- Running a Simulation 92
- Chapter 5: Testbench 5–7 93
- Testbench Time-Out 94
- Verilog HDL 95
- 5–10 Chapter 5: Testbench 96
- Chapter 5: Testbench 5–11 97
- Chapter 5: Testbench 5–13 99
- 5–14 Chapter 5: Testbench 100
- Status Monitors (pin_mon) 101
- Pin_mon Tasks - Verilog HDL 102
- Chapter 5: Testbench 5–17 103
- 5–18 Chapter 5: Testbench 104
- Chapter 5: Testbench 5–19 105
- 5–20 Chapter 5: Testbench 106
- Chapter 5: Testbench 5–21 107
- Additional Information 108
- Typographic Conventions 109
- Visual Cue Meaning 110
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