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Chapter 3: Parameter Settings 3–29
Optimizing the Implementation
January 2014 Altera Corporation SerialLite II MegaCore Function
User Guide
Error signals, such as
txrdp_err
and
txhpp_err
, are asserted by user logic. When
txrdp_err
is asserted with
txrdp_eop
, the packet is marked with the end of bad
packet (EBP) marker. The
txrdp_err
signal is ignored when it is not asserted with
txrdp_eop
.
When the
txhpp_err
is asserted and the Retry-on-error feature is turned off, the
packet is marked with the EBP marker. When the
txhpp_err
is asserted and the Retry-
on-error feature is turned on, the packet is not transmitted and is silently dropped.
Optimizing the Implementation
There are a number of steps you can take to optimize your design, depending on your
goals. The features selected in your SerialLite II configuration have a substantial
impact on both resource utilization and performance. Because of the number of
different combinations of options that are available, it is difficult to generalize the
performance or resource requirements of a design. In addition, the performance of a
SerialLite II link in isolation is different from the performance of the same link
instantiated alongside large amounts of other logic in the device.
For the most part, the steps you take to improve performance or resource utilization
are similar to the steps you would take for any other design. The following
suggestions are intended to provide ideas, but should not be considered an
exhaustive list.
Improving Performance
Performance is the factor that depends most on what other logic exists in the device. If
the SerialLite II MegaCore function is competing with other logic for routing
resources, inefficient routing could compromise speed. The following sections
describe some things that can be considered if speed is an issue.
Data
■ Invalid 8b/10b codes groups
■ Running disparity errors
■ Unsupported valid code groups
■ Link protocol violation
■ LMP with BIP error
■ CRC error
■ Unexpected channel number
■ Out of order packet
■ Out of order acknowledgment (if retry-
on-error enabled)
Two possibilities:
■ If Retry-on-error is enabled
and the packet is a priority
packet, request
retransmission.
■ Otherwise, mark the packet as
bad and forward it to the user
link layer.
Packets Marked
Bad
{EBP} marked packet
Received packet is marked as bad
via the
rxrdp_err
or
rxhpp_err
signals, and forwarded to the
user link layer.
Table 3–12. Error Summary (Part 2 of 2)
Error Type Cause Action
- User Guide 1
- Contents 3
- Chapter 5. Testbench 5
- Release Information 6
- Device Family Support 6
- Features 7
- General Description 8
- (EP2GX90FF1508C3) 10
- Notes to Table 1–3: 11
- Installation and Licensing 13
- OpenCore Plus Evaluation 14
- Simulate with Testbench 16
- Design Flow 17
- Parameterize 18
- Set Up Simulation 21
- Generate Files 21
- Simulate the Design 22
- Instantiate the MegaCore 22
- Specify Constraints 22
- Compile and Program 23
- 3. Parameter Settings 24
- Link Consistency 25
- Physical Layer Configuration 25
- Transfer size 26
- Reference Clock Frequency 26
- Port Type 27
- Notes to Figure 3–3: 28
- Note to Figure 3–4: 28
- Note to Figure 3–5: 29
- Notes to Figure 3–6: 29
- Self Synchronized Link Up 30
- Number of Lanes 31
- Scramble 32
- De-Scramble 32
- Broadcast Mode 32
- Clock Compensation 33
- Link Layer Configuration 34
- Retry-on-error Disabled 35
- Retry-on-error Enabled 35
- Segment Size 35
- Retry-on-error 36
- Retry-on-error Responses 37
- Flow Control 38
- Notes to Figure 3–12: 41
- Notes to Table 3–6: 42
- Transmit/Receive FIFO Buffers 43
- FIFO Buffer Size 44
- FIFO Buffer Structure 44
- 16-Bit Versus 32-Bit CRC 46
- Transceiver Configuration 47
- Transmitter Buffer Power (V 48
- Equalizer Control Settings 48
- Bandwidth Mode 48
- Starting Channel number 49
- ALTGX Support Signals 50
- Error Handling 51
- Optimizing the Implementation 52
- Feature Selection 53
- Running Different Seeds 53
- Limiting Fanout 53
- Floorplanning 53
- Minimizing Memory Utilization 54
- 4. Functional Description 55
- Atlantic Interface 56
- High-Speed Serial Interface 57
- Clocks and Data Rates 58
- External Clock Modes 59
- SerialLite II Deskew Support 60
- Note to Figure 4–6: 61
- Note to Figure 4–7: 62
- Note to Figure 4–8: 63
- Note to Figure 4–9: 64
- Note to Figure 4–10: 65
- Note to Figure 4–11: 66
- Note to Figure 4–14: 69
- Initialization and Restart 71
- Multiple Core Configuration 72
- Compilation 73
- Testbench 74
- Simulation Support 74
- Notes to Table 4–5: 77
- Notes to Table 4–6: 79
- Notes to Table 4–7: 81
- Notes to Table 4–8: 81
- Notes to Table 4–9: 82
- Note to Table 4–10: 84
- MegaCore Verification 85
- 5. Testbench 87
- Testbench Specifications 88
- Notes to Figure 5–1: 89
- 5–4 Chapter 5: Testbench 90
- Simulation Flow 91
- Running a Simulation 92
- Chapter 5: Testbench 5–7 93
- Testbench Time-Out 94
- Verilog HDL 95
- 5–10 Chapter 5: Testbench 96
- Chapter 5: Testbench 5–11 97
- Chapter 5: Testbench 5–13 99
- 5–14 Chapter 5: Testbench 100
- Status Monitors (pin_mon) 101
- Pin_mon Tasks - Verilog HDL 102
- Chapter 5: Testbench 5–17 103
- 5–18 Chapter 5: Testbench 104
- Chapter 5: Testbench 5–19 105
- 5–20 Chapter 5: Testbench 106
- Chapter 5: Testbench 5–21 107
- Additional Information 108
- Typographic Conventions 109
- Visual Cue Meaning 110
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