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3–26 Chapter 3: Parameter Settings
Transceiver Configuration
SerialLite II MegaCore Function January 2014 Altera Corporation
User Guide
■ The high bandwidth setting provides a faster lock time and tracks more jitter on
the input clock source which passes it through the PLL to help reject noise from the
voltage control oscillator (VCO) and power supplies.
■ The low bandwidth setting filters out more high frequency input clock jitter, but
increases lock time. The PLL is set to the low setting by default.
■ The medium setting balances the lock time and noise rejection/jitter filtering
between the high and low settings.
If the number of lanes in the transmit or receive direction is equal to zero, the
bandwidth mode for that direction is disabled. This parameter is also disabled for
Arria II GX devices.
Starting Channel number
The range for the dynamic reconfiguration starting channel number setting is 0 to 380
for Stratix IV GX devices. These ranges are in multiples of four because the dynamic
reconfiguration interface is per transceiver block. The range 0 to 380 is the logical
channel address, based purely on the number of possible transceiver instances. This
parameter is not applicable for Arria II GX devices.
Instantiating a Transceiver Reconfiguration Block
When you use an Arria II GX, Arria V, Cyclone V, S tr at ix I V, or a S tr at ix V d e v i c e , y o u
can instantiate a transceiver reconfiguration block that dynamically changes the
following physical media attachment (PMA) settings:
■ Pre-emphasis
■ Equalization
■ V
OD
■ Offset cancelation
1 For analog settings, there are no restrictions on using dynamic reconfiguration.
When you use a transceiver-based device, the ALTGX interface allows you to modify
the parameter interface with a reconfiguration block. The
altgx_reconfig
block is not
instantiated, but the MegaWizard-generated wrapper provides the ports that interface
to the
altgx_reconfig
block. If you choose to use an
altgx_reconfig
block, you must
instantiate the
altgx_reconfig
block and connect the associated signals to the
corresponding SerialLite II MegaCore function top-level signals (tie the
reconfig_fromgxb
,
reconfig_clk
, and
reconfig_togxb
ports to the
altgx_reconfig
block).
1 You must instantiate the transceiver reconfiguration block on an Arria II GX or a
Stratix IV device, because these device transceivers require offset cancelation. Your
Arria II GX or Stratix IV design can compile without the dynamic reconfiguration
block but it cannot function correctly in hardware.
f For more information about the following topics, refer to the respective documents:
- User Guide 1
- Contents 3
- Chapter 5. Testbench 5
- Release Information 6
- Device Family Support 6
- Features 7
- General Description 8
- (EP2GX90FF1508C3) 10
- Notes to Table 1–3: 11
- Installation and Licensing 13
- OpenCore Plus Evaluation 14
- Simulate with Testbench 16
- Design Flow 17
- Parameterize 18
- Set Up Simulation 21
- Generate Files 21
- Simulate the Design 22
- Instantiate the MegaCore 22
- Specify Constraints 22
- Compile and Program 23
- 3. Parameter Settings 24
- Link Consistency 25
- Physical Layer Configuration 25
- Transfer size 26
- Reference Clock Frequency 26
- Port Type 27
- Notes to Figure 3–3: 28
- Note to Figure 3–4: 28
- Note to Figure 3–5: 29
- Notes to Figure 3–6: 29
- Self Synchronized Link Up 30
- Number of Lanes 31
- Scramble 32
- De-Scramble 32
- Broadcast Mode 32
- Clock Compensation 33
- Link Layer Configuration 34
- Retry-on-error Disabled 35
- Retry-on-error Enabled 35
- Segment Size 35
- Retry-on-error 36
- Retry-on-error Responses 37
- Flow Control 38
- Notes to Figure 3–12: 41
- Notes to Table 3–6: 42
- Transmit/Receive FIFO Buffers 43
- FIFO Buffer Size 44
- FIFO Buffer Structure 44
- 16-Bit Versus 32-Bit CRC 46
- Transceiver Configuration 47
- Transmitter Buffer Power (V 48
- Equalizer Control Settings 48
- Bandwidth Mode 48
- Starting Channel number 49
- ALTGX Support Signals 50
- Error Handling 51
- Optimizing the Implementation 52
- Feature Selection 53
- Running Different Seeds 53
- Limiting Fanout 53
- Floorplanning 53
- Minimizing Memory Utilization 54
- 4. Functional Description 55
- Atlantic Interface 56
- High-Speed Serial Interface 57
- Clocks and Data Rates 58
- External Clock Modes 59
- SerialLite II Deskew Support 60
- Note to Figure 4–6: 61
- Note to Figure 4–7: 62
- Note to Figure 4–8: 63
- Note to Figure 4–9: 64
- Note to Figure 4–10: 65
- Note to Figure 4–11: 66
- Note to Figure 4–14: 69
- Initialization and Restart 71
- Multiple Core Configuration 72
- Compilation 73
- Testbench 74
- Simulation Support 74
- Notes to Table 4–5: 77
- Notes to Table 4–6: 79
- Notes to Table 4–7: 81
- Notes to Table 4–8: 81
- Notes to Table 4–9: 82
- Note to Table 4–10: 84
- MegaCore Verification 85
- 5. Testbench 87
- Testbench Specifications 88
- Notes to Figure 5–1: 89
- 5–4 Chapter 5: Testbench 90
- Simulation Flow 91
- Running a Simulation 92
- Chapter 5: Testbench 5–7 93
- Testbench Time-Out 94
- Verilog HDL 95
- 5–10 Chapter 5: Testbench 96
- Chapter 5: Testbench 5–11 97
- Chapter 5: Testbench 5–13 99
- 5–14 Chapter 5: Testbench 100
- Status Monitors (pin_mon) 101
- Pin_mon Tasks - Verilog HDL 102
- Chapter 5: Testbench 5–17 103
- 5–18 Chapter 5: Testbench 104
- Chapter 5: Testbench 5–19 105
- 5–20 Chapter 5: Testbench 106
- Chapter 5: Testbench 5–21 107
- Additional Information 108
- Typographic Conventions 109
- Visual Cue Meaning 110
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