Altera SerialLite II IP Core Manual de usuario Pagina 78
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Valorado. / 5. Basado en revisión del cliente
4–24 Chapter 4: Functional Description
Signals
SerialLite II MegaCore Function January 2014 Altera Corporation
User Guide
err_tc_pcfifo_uflw
[txnl-
1:0
]
Output
tx_coreclock
Interface/phase compensation FIFO buffer
underflow signal (Arria II GX and Stratix IV devices
only).
err_tc_pcfifo_oflw
[txnl-
1:0
]
Output
tx_coreclock
Interface/phase compensation FIFO buffer overflow
signal (Arria II GX and Stratix IV devices only).
stat_rr_sigdet
[rxnl-
1:0
]
Output
rrefclk
This signal is for debugging purposes only and can
be ignored.
stat_rr_gxsync
(5)
[srx-
1:0
]
Output
rrefclk
Gives the status of the pattern detector and word
aligner.
stat_rr_rxlocked
(5)
[rxnl-
1:0
]
Output
rrefclk
Receiver PLL locked signal. Indicates whether or
not the receiver PLL is phase locked to the CRU
reference clock. When the PLL locks to data, which
happens some time after the transceiver’s
rx_freqlocked
signal is asserted high, this signal
has little meaning because it only indicates lock to
the reference clock. This signal is active high for
Arria II GX and Stratix IV devices.
stat_rr_freqlock
[rxnl-1:0]
Output
rrefclk
Frequency locked signal from the CRU. Indicates
whether the transceiver block receiver channel is
locked to the data mode in the
rxin
port.
stat_rr_pattdet
[srx-1:0]
Output
rrefclk
Pattern detection signal
reconfig_fromgxb
(3),
(5)
Arria II GX or Stratix IV GX:
[recon_quad*17-1:0]
Output
reconfig_clk
(4)
ALTGX Reconfig from the GXB Bus.
This signal is connected to the
reconfig_fromgxb
port on the
altgx_reconfig
module. If you use
Arria II GX or Stratix IV device, you must connect
this output to the
altgx_reconfig
module for
offset cancelation.
reconfig_togxb
(5)
Arria II GX or Stratix IV GX:
[3:0]
Input
reconfig_clk
ALTGX Reconfig to the GXB Bus.
This signal is connected to the
reconfig_togxb
port on the
altgx_reconfig
module. If you use
Arria II GX or Stratix IV device, you must connect
this output to the
altgx_reconfig
module for
offset cancelation.
reconfig_clk
Input —
ALTGX Reconfig Clock to the GXB.
This signal is connected to the
reconfig_clk
port
on the
altgx_reconfig
module. If you use
Arria II GX or Stratix IV device, you must connect
this output to the
altgx_reconfig
module for
offset cancelation.
cal_blk_clk
(5)
Input —
Calibration clock for the termination resistor
calibration block. The frequency range of
cal_blk_clk
is 10 to 125 MHz.
Table 4–6. Transceiver Megafunction Signals (Part 2 of 3)
Signal
(1)
,
(2)
Direction Clock Domain Description
- User Guide 1
- Contents 3
- Chapter 5. Testbench 5
- Release Information 6
- Device Family Support 6
- Features 7
- General Description 8
- (EP2GX90FF1508C3) 10
- Notes to Table 1–3: 11
- Installation and Licensing 13
- OpenCore Plus Evaluation 14
- Simulate with Testbench 16
- Design Flow 17
- Parameterize 18
- Set Up Simulation 21
- Generate Files 21
- Simulate the Design 22
- Instantiate the MegaCore 22
- Specify Constraints 22
- Compile and Program 23
- 3. Parameter Settings 24
- Link Consistency 25
- Physical Layer Configuration 25
- Transfer size 26
- Reference Clock Frequency 26
- Port Type 27
- Notes to Figure 3–3: 28
- Note to Figure 3–4: 28
- Note to Figure 3–5: 29
- Notes to Figure 3–6: 29
- Self Synchronized Link Up 30
- Number of Lanes 31
- Scramble 32
- De-Scramble 32
- Broadcast Mode 32
- Clock Compensation 33
- Link Layer Configuration 34
- Retry-on-error Disabled 35
- Retry-on-error Enabled 35
- Segment Size 35
- Retry-on-error 36
- Retry-on-error Responses 37
- Flow Control 38
- Notes to Figure 3–12: 41
- Notes to Table 3–6: 42
- Transmit/Receive FIFO Buffers 43
- FIFO Buffer Size 44
- FIFO Buffer Structure 44
- 16-Bit Versus 32-Bit CRC 46
- Transceiver Configuration 47
- Transmitter Buffer Power (V 48
- Equalizer Control Settings 48
- Bandwidth Mode 48
- Starting Channel number 49
- ALTGX Support Signals 50
- Error Handling 51
- Optimizing the Implementation 52
- Feature Selection 53
- Running Different Seeds 53
- Limiting Fanout 53
- Floorplanning 53
- Minimizing Memory Utilization 54
- 4. Functional Description 55
- Atlantic Interface 56
- High-Speed Serial Interface 57
- Clocks and Data Rates 58
- External Clock Modes 59
- SerialLite II Deskew Support 60
- Note to Figure 4–6: 61
- Note to Figure 4–7: 62
- Note to Figure 4–8: 63
- Note to Figure 4–9: 64
- Note to Figure 4–10: 65
- Note to Figure 4–11: 66
- Note to Figure 4–14: 69
- Initialization and Restart 71
- Multiple Core Configuration 72
- Compilation 73
- Testbench 74
- Simulation Support 74
- Notes to Table 4–5: 77
- Notes to Table 4–6: 79
- Notes to Table 4–7: 81
- Notes to Table 4–8: 81
- Notes to Table 4–9: 82
- Note to Table 4–10: 84
- MegaCore Verification 85
- 5. Testbench 87
- Testbench Specifications 88
- Notes to Figure 5–1: 89
- 5–4 Chapter 5: Testbench 90
- Simulation Flow 91
- Running a Simulation 92
- Chapter 5: Testbench 5–7 93
- Testbench Time-Out 94
- Verilog HDL 95
- 5–10 Chapter 5: Testbench 96
- Chapter 5: Testbench 5–11 97
- Chapter 5: Testbench 5–13 99
- 5–14 Chapter 5: Testbench 100
- Status Monitors (pin_mon) 101
- Pin_mon Tasks - Verilog HDL 102
- Chapter 5: Testbench 5–17 103
- 5–18 Chapter 5: Testbench 104
- Chapter 5: Testbench 5–19 105
- 5–20 Chapter 5: Testbench 106
- Chapter 5: Testbench 5–21 107
- Additional Information 108
- Typographic Conventions 109
- Visual Cue Meaning 110
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