Altera SerialLite II IP Core Manual de usuario Pagina 75
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Chapter 4: Functional Description 4–21
MegaCore Configuration for Arria V, Cyclone V, and Stratix V Devices
January 2014 Altera Corporation SerialLite II MegaCore Function
User Guide
f For more information about the Custom PHY IP core ports, refer to the Altera
Transceiver PHY IP Core User Guide.
Extra Signals Between SerialLite II MegaCore and Custom PHY IP Core
The SerialLite II MegaCore function includes new signals to interface with the
Custom PHY IP core for data communication.
Create tx_coreclkin port
Provides transceiver clock output to the
tx_coreclk
signal in the
SerialLite II MegaCore.
For Arria V, Cyclone V, and Stratix V designs with more than 1
channel, connect transceiver PHY
tx_clkout(0)
to
tx_coreclkin (N-1:0)
.
Required
Create rx_recovered_clk port Provides a recovered clock output for the transceiver. Off
Create optional ports
Provide the following ports:
■
tx_forceelecidle
■
rx_is_lockedtoref
■
rx_is_lockedtodata
■
rx_signaldetect
Optional
Avalon data interfaces Enables support for Avalon-Streaming (ST) interface. Optional
Enable embedded reset controller Enables the controller to reset the transceiver. Required
Create optional word aligner status
ports
Provide the following word aligner status ports for the transceiver:
■
rx_syncstatus
■
rx_patterndetect
Optional
Enable run length violation checking
Enables run length violation check to the
err_rr_rlv
signal in the
SerialLite II MegaCore.
Required
Enable rate match FIFO Enables support for rate match FIFO. Optional
Create optional rate match FIFO
status ports
Enable the status ports for rate match FIFO. Optional
Enable 8B/10B encoder/decoder
Provide the following ports:
■ rx_runningdisp—provides running disparity status to the
err_rr_disp
signal in the SerialLite II core.
■ rx_datak—indicates whether the rx_parallel_data output port
contains data or control symbol.
Required
Enable manual disparity control Enables manual disparity control for the 8B/10B encoder/decoder. Off
Create optional 8B/10B status ports
Provide the following status ports for the 8B/10B encoder/decoder
operation:
■
rx_errdetect
■
rx_disperr
Optional
Enable byte ordering block Enables byte ordering pattern configuration. Off
Enable byte ordering block manual
control
Provides manual control for the byte ordering block. Off
Allow PLL/CDR reconfiguration Enables support for dynamic reconfiguration of Tx PLL and Rx CDR. Off
Table 4–3. Custom PHY IP Core Settings (Part 2 of 2)
Option Description Setting
- User Guide 1
- Contents 3
- Chapter 5. Testbench 5
- Release Information 6
- Device Family Support 6
- Features 7
- General Description 8
- (EP2GX90FF1508C3) 10
- Notes to Table 1–3: 11
- Installation and Licensing 13
- OpenCore Plus Evaluation 14
- Simulate with Testbench 16
- Design Flow 17
- Parameterize 18
- Set Up Simulation 21
- Generate Files 21
- Simulate the Design 22
- Instantiate the MegaCore 22
- Specify Constraints 22
- Compile and Program 23
- 3. Parameter Settings 24
- Link Consistency 25
- Physical Layer Configuration 25
- Transfer size 26
- Reference Clock Frequency 26
- Port Type 27
- Notes to Figure 3–3: 28
- Note to Figure 3–4: 28
- Note to Figure 3–5: 29
- Notes to Figure 3–6: 29
- Self Synchronized Link Up 30
- Number of Lanes 31
- Scramble 32
- De-Scramble 32
- Broadcast Mode 32
- Clock Compensation 33
- Link Layer Configuration 34
- Retry-on-error Disabled 35
- Retry-on-error Enabled 35
- Segment Size 35
- Retry-on-error 36
- Retry-on-error Responses 37
- Flow Control 38
- Notes to Figure 3–12: 41
- Notes to Table 3–6: 42
- Transmit/Receive FIFO Buffers 43
- FIFO Buffer Size 44
- FIFO Buffer Structure 44
- 16-Bit Versus 32-Bit CRC 46
- Transceiver Configuration 47
- Transmitter Buffer Power (V 48
- Equalizer Control Settings 48
- Bandwidth Mode 48
- Starting Channel number 49
- ALTGX Support Signals 50
- Error Handling 51
- Optimizing the Implementation 52
- Feature Selection 53
- Running Different Seeds 53
- Limiting Fanout 53
- Floorplanning 53
- Minimizing Memory Utilization 54
- 4. Functional Description 55
- Atlantic Interface 56
- High-Speed Serial Interface 57
- Clocks and Data Rates 58
- External Clock Modes 59
- SerialLite II Deskew Support 60
- Note to Figure 4–6: 61
- Note to Figure 4–7: 62
- Note to Figure 4–8: 63
- Note to Figure 4–9: 64
- Note to Figure 4–10: 65
- Note to Figure 4–11: 66
- Note to Figure 4–14: 69
- Initialization and Restart 71
- Multiple Core Configuration 72
- Compilation 73
- Testbench 74
- Simulation Support 74
- Notes to Table 4–5: 77
- Notes to Table 4–6: 79
- Notes to Table 4–7: 81
- Notes to Table 4–8: 81
- Notes to Table 4–9: 82
- Note to Table 4–10: 84
- MegaCore Verification 85
- 5. Testbench 87
- Testbench Specifications 88
- Notes to Figure 5–1: 89
- 5–4 Chapter 5: Testbench 90
- Simulation Flow 91
- Running a Simulation 92
- Chapter 5: Testbench 5–7 93
- Testbench Time-Out 94
- Verilog HDL 95
- 5–10 Chapter 5: Testbench 96
- Chapter 5: Testbench 5–11 97
- Chapter 5: Testbench 5–13 99
- 5–14 Chapter 5: Testbench 100
- Status Monitors (pin_mon) 101
- Pin_mon Tasks - Verilog HDL 102
- Chapter 5: Testbench 5–17 103
- 5–18 Chapter 5: Testbench 104
- Chapter 5: Testbench 5–19 105
- 5–20 Chapter 5: Testbench 106
- Chapter 5: Testbench 5–21 107
- Additional Information 108
- Typographic Conventions 109
- Visual Cue Meaning 110
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