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Chapter 3: Parameter Settings 3–23
Link Layer Configuration
January 2014 Altera Corporation SerialLite II MegaCore Function
User Guide
The threshold levels on both the transmitter and receiver Atlantic FIFO buffers differ
according to implementation. They may depend on the data traffic, the FIFO depth,
and the clock frequencies for read and write. Based on your design, you can gauge the
usual fill level of the FIFO buffers and determine the appropriate threshold levels.
Data Integrity Protection: CRC
If you need error protection, you may add CRC checking to your packet. The CRC is
automatically generated in transmission and is automatically checked on reception.
On the data port, a CRC check failure results in the packet being marked as bad using
the
rxrdp_err/rxhpp_err
signal on the Atlantic interface. You decide independently
for each port whether CRC usage is enabled.
16-Bit Versus 32-Bit CRC
The SerialLite II MegaCore function supports both 16-bit and 32-bit CRC algorithms.
You decide which CRC algorithm to use independently for each port. The 16-bit
algorithm generates a two-byte result, and uses the following polynomial equation:
G(x) = X
16
+ X
12
+ X
5
+ 1
The 32-bit algorithm generates a four-byte result, and uses the following polynomial
equation:
G(x) = X
32
+ X
26
+ X
23
+ X
22
+ X
16
+ X
12
+ X
11
+ X
10
+ X
8
+ X
7
+ X
5
+ X
4
+ X
2
+ X + 1
The 16-bit version provides excellent protection for packets smaller than about 1
KBytes. For larger packets, CRC-32 can be considered, but it requires significantly
more logic, especially in implementations requiring many lanes. At 16 lanes, CRC-32
logic may constitute as much as half of the logic of the entire SerialLite II instantiation.
Therefore, CRC-32 should only be used when absolutely necessary.
Table 3–8 and Table 3–9 show the different CRC options.
Table 3–8. CRC Options
Option Description
Enabled CRC logic is created. CRC usage is specified independently for each port.
Disabled
CRC logic is not created. CRC usage is specified independently for each
port. This is the default CRC setting.
Table 3–9. CRC Type Options
Option Description
16-bit
Generates a two-byte CRC. Adequate for packets of around 1 KBytes or
smaller. This is the default algorithm once CRC usage has been enabled.
32-bit
Generates a 4-byte CRC. Should only be used for packets larger than about
1 KBytes or when extreme protection is required, because it is
resource-intensive.
- User Guide 1
- Contents 3
- Chapter 5. Testbench 5
- Release Information 6
- Device Family Support 6
- Features 7
- General Description 8
- (EP2GX90FF1508C3) 10
- Notes to Table 1–3: 11
- Installation and Licensing 13
- OpenCore Plus Evaluation 14
- Simulate with Testbench 16
- Design Flow 17
- Parameterize 18
- Set Up Simulation 21
- Generate Files 21
- Simulate the Design 22
- Instantiate the MegaCore 22
- Specify Constraints 22
- Compile and Program 23
- 3. Parameter Settings 24
- Link Consistency 25
- Physical Layer Configuration 25
- Transfer size 26
- Reference Clock Frequency 26
- Port Type 27
- Notes to Figure 3–3: 28
- Note to Figure 3–4: 28
- Note to Figure 3–5: 29
- Notes to Figure 3–6: 29
- Self Synchronized Link Up 30
- Number of Lanes 31
- Scramble 32
- De-Scramble 32
- Broadcast Mode 32
- Clock Compensation 33
- Link Layer Configuration 34
- Retry-on-error Disabled 35
- Retry-on-error Enabled 35
- Segment Size 35
- Retry-on-error 36
- Retry-on-error Responses 37
- Flow Control 38
- Notes to Figure 3–12: 41
- Notes to Table 3–6: 42
- Transmit/Receive FIFO Buffers 43
- FIFO Buffer Size 44
- FIFO Buffer Structure 44
- 16-Bit Versus 32-Bit CRC 46
- Transceiver Configuration 47
- Transmitter Buffer Power (V 48
- Equalizer Control Settings 48
- Bandwidth Mode 48
- Starting Channel number 49
- ALTGX Support Signals 50
- Error Handling 51
- Optimizing the Implementation 52
- Feature Selection 53
- Running Different Seeds 53
- Limiting Fanout 53
- Floorplanning 53
- Minimizing Memory Utilization 54
- 4. Functional Description 55
- Atlantic Interface 56
- High-Speed Serial Interface 57
- Clocks and Data Rates 58
- External Clock Modes 59
- SerialLite II Deskew Support 60
- Note to Figure 4–6: 61
- Note to Figure 4–7: 62
- Note to Figure 4–8: 63
- Note to Figure 4–9: 64
- Note to Figure 4–10: 65
- Note to Figure 4–11: 66
- Note to Figure 4–14: 69
- Initialization and Restart 71
- Multiple Core Configuration 72
- Compilation 73
- Testbench 74
- Simulation Support 74
- Notes to Table 4–5: 77
- Notes to Table 4–6: 79
- Notes to Table 4–7: 81
- Notes to Table 4–8: 81
- Notes to Table 4–9: 82
- Note to Table 4–10: 84
- MegaCore Verification 85
- 5. Testbench 87
- Testbench Specifications 88
- Notes to Figure 5–1: 89
- 5–4 Chapter 5: Testbench 90
- Simulation Flow 91
- Running a Simulation 92
- Chapter 5: Testbench 5–7 93
- Testbench Time-Out 94
- Verilog HDL 95
- 5–10 Chapter 5: Testbench 96
- Chapter 5: Testbench 5–11 97
- Chapter 5: Testbench 5–13 99
- 5–14 Chapter 5: Testbench 100
- Status Monitors (pin_mon) 101
- Pin_mon Tasks - Verilog HDL 102
- Chapter 5: Testbench 5–17 103
- 5–18 Chapter 5: Testbench 104
- Chapter 5: Testbench 5–19 105
- 5–20 Chapter 5: Testbench 106
- Chapter 5: Testbench 5–21 107
- Additional Information 108
- Typographic Conventions 109
- Visual Cue Meaning 110
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