Altera SerialLite II IP Core Manual de usuario Pagina 44
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Valorado. / 5. Basado en revisión del cliente
Chapter 3: Parameter Settings 3–21
Link Layer Configuration
January 2014 Altera Corporation SerialLite II MegaCore Function
User Guide
FIFO Buffer Size
The size of the FIFO buffers is based on the factors listed in Table 3–7 on page 3–20.
FIFO Buffer Structure
Figure 3–13 shows the Atlantic FIFO buffer structure.
The FIFO buffer threshold low (FTL),
ctl_rxrdp_ftl/ctl_rxhpp_ftl,
value for
receiver variations controls when the
rxrdp_dav/rxhpp_dav
signals are asserted for
the read side of the FIFO buffer, respectively. If the fill level of the buffer is higher than
the FTL value, the
rxrdp_dav/rxhpp_dav
signal is asserted indicating that there is a
burst of data available.
1 There is no requirement to wait for the
rxrdp_dav/rxhpp_dav
signal to be asserted;
you can read from the buffer at any time by asserting the
rxrdp_ena/rxhpp_ena
signal
at all times and qualifying the data with the
rxrdp_val/rxhpp_val
signal. The FIFO
buffer has built-in underflow protection, such that an underflow condition does not
exit.
Table 3–7. Factors Affecting Receive FIFO Buffer Size
Factor Description
Flow control
If flow control is enabled, the FIFO buffer size should change to
account for the thresholds that must be set.
Pause duration
When optimizing against starvation during flow control, the pause
duration affects the FIFO buffer size.
Number of packets (and
packet sizes)
If you want to use a store-and-forward FIFO (using the
eop_dav
and a high threshold), the FIFO must be big enough to hold a full
packet at minimum.
Wire delay and bit rate
The wire propagation delay and the bit rate change the wire latency,
which must be accommodated if flow control is used.
Figure 3–13. Atlantic FIFO Buffer Structure
Width set automatically
Threshold
Headroom
FTL/FTH
Total
depth
- User Guide 1
- Contents 3
- Chapter 5. Testbench 5
- Release Information 6
- Device Family Support 6
- Features 7
- General Description 8
- (EP2GX90FF1508C3) 10
- Notes to Table 1–3: 11
- Installation and Licensing 13
- OpenCore Plus Evaluation 14
- Simulate with Testbench 16
- Design Flow 17
- Parameterize 18
- Set Up Simulation 21
- Generate Files 21
- Simulate the Design 22
- Instantiate the MegaCore 22
- Specify Constraints 22
- Compile and Program 23
- 3. Parameter Settings 24
- Link Consistency 25
- Physical Layer Configuration 25
- Transfer size 26
- Reference Clock Frequency 26
- Port Type 27
- Notes to Figure 3–3: 28
- Note to Figure 3–4: 28
- Note to Figure 3–5: 29
- Notes to Figure 3–6: 29
- Self Synchronized Link Up 30
- Number of Lanes 31
- Scramble 32
- De-Scramble 32
- Broadcast Mode 32
- Clock Compensation 33
- Link Layer Configuration 34
- Retry-on-error Disabled 35
- Retry-on-error Enabled 35
- Segment Size 35
- Retry-on-error 36
- Retry-on-error Responses 37
- Flow Control 38
- Notes to Figure 3–12: 41
- Notes to Table 3–6: 42
- Transmit/Receive FIFO Buffers 43
- FIFO Buffer Size 44
- FIFO Buffer Structure 44
- 16-Bit Versus 32-Bit CRC 46
- Transceiver Configuration 47
- Transmitter Buffer Power (V 48
- Equalizer Control Settings 48
- Bandwidth Mode 48
- Starting Channel number 49
- ALTGX Support Signals 50
- Error Handling 51
- Optimizing the Implementation 52
- Feature Selection 53
- Running Different Seeds 53
- Limiting Fanout 53
- Floorplanning 53
- Minimizing Memory Utilization 54
- 4. Functional Description 55
- Atlantic Interface 56
- High-Speed Serial Interface 57
- Clocks and Data Rates 58
- External Clock Modes 59
- SerialLite II Deskew Support 60
- Note to Figure 4–6: 61
- Note to Figure 4–7: 62
- Note to Figure 4–8: 63
- Note to Figure 4–9: 64
- Note to Figure 4–10: 65
- Note to Figure 4–11: 66
- Note to Figure 4–14: 69
- Initialization and Restart 71
- Multiple Core Configuration 72
- Compilation 73
- Testbench 74
- Simulation Support 74
- Notes to Table 4–5: 77
- Notes to Table 4–6: 79
- Notes to Table 4–7: 81
- Notes to Table 4–8: 81
- Notes to Table 4–9: 82
- Note to Table 4–10: 84
- MegaCore Verification 85
- 5. Testbench 87
- Testbench Specifications 88
- Notes to Figure 5–1: 89
- 5–4 Chapter 5: Testbench 90
- Simulation Flow 91
- Running a Simulation 92
- Chapter 5: Testbench 5–7 93
- Testbench Time-Out 94
- Verilog HDL 95
- 5–10 Chapter 5: Testbench 96
- Chapter 5: Testbench 5–11 97
- Chapter 5: Testbench 5–13 99
- 5–14 Chapter 5: Testbench 100
- Status Monitors (pin_mon) 101
- Pin_mon Tasks - Verilog HDL 102
- Chapter 5: Testbench 5–17 103
- 5–18 Chapter 5: Testbench 104
- Chapter 5: Testbench 5–19 105
- 5–20 Chapter 5: Testbench 106
- Chapter 5: Testbench 5–21 107
- Additional Information 108
- Typographic Conventions 109
- Visual Cue Meaning 110
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