Altera Transceiver PHY IP Core Manual de usuario Pagina 605
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Description
When set to DYNAMIC_CTL, the PCS block controls the V
OD
and pre-emphasis coefficients for PCI
Express. When this assignment is set to RAM_CTL the V
OD
and pre-emphasis are controlled by other
assignments, such as XCVR_TX_PRE_EMP_1ST_POST_TAP.
Options
• DYNAMIC_CTL: for PCI Express
• RAM_CTL: for all other protocols
Assign To
Pin - TX serial data
Analog Settings for Arria V GZ Devices
Analog Settings for Arria V GZ Devices
This section lists the analog parameters for Arria V GZ devices whose original values are place holders for
the values that match your electrical board specification. In the following table, the default value of an
analog parameter is shown in bold type. The parameters are listed in alphabetical order.
The following table lists the analog parameters with global or computed default values. You may want to
optimize some of these settings. The default value is shown in bold type. For computed analog
parameters, the default value listed is for the initial setting, not the recomputed setting. The parameters
are listed in alphabetical order.
For more information about the Pin Planner, refer to About the Pin Planner in Quartus II Help. For more
information about the Assignment Editor, refer to About the Assignment Editor in Quartus II Help.
For more information about Quartus II Settings, refer to Quartus II Settings File Manual.
Related Information
• PCI Express Card Electromechanical Specification Rev. 2.0
• Device Datasheet for Arria V Devices
• About the Pin Planner
• About the Assignment Editor
• Quartus II Settings File Manual
XCVR_IO_PIN_TERMINATION
Pin Planner and Assignment Editor Name
Transceiver I/O Pin Termination
Description
Specifies the intended on-chip termination value for the specified transceiver pin. Use External Resistor if
you intend to use off-chip termination.
UG-01080
2015.01.19
Analog Settings for Arria V GZ Devices
19-11
Analog Parameters Set Using QSF Assignments
Altera Corporation
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- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Altera Corporation 10
- Native Transceiver PHYs 12
- Transceiver PHY Modules 15
- Resetting the Transceiver PHY 16
- File Name Description 18
- Unsupported Features 20
- Getting Started Overview 21
- Design Flows 22
- Specifying Parameters 23
- Simulate the IP Core 24
- 10GBASE-R PHY IP Core 25
- Arria V GT 10GBASE-R 27
- Transceiver Protocol 28
- General Option Parameters 33
- 10GBASE-R PHY Interfaces 37
- 10GBASE-R PHY Data Interfaces 38
- Reset Control and Power Down 46
- Signal Name Directio 53
- 1588 Delay Requirements 54
- 10GBASE-R Parameters 63
- Reconfig 67
- 10BASE-KR PHY Interfaces 75
- Daisy-Chain Interface Signals 83
- Bit R/W Name Description 100
- PMA Registers 103
- PCS Registers 104
- Creating a 10GBASE-KR Design 105
- Editing a 10GBASE-KR MIF File 106
- Send Feedback 107
- Design Example 108
- SDC Timing Constraints 109
- Acronyms 109
- UG-01080 110
- Subscribe 110
- Related Information 111
- Item Description 111
- Device Family Support 112
- 1GbE Parameters 113
- Speed Detection Parameters 114
- PHY Analog Parameters 115
- 1G/10GbE PHY Interfaces 116
- 2015.01.19 117
- 1G/10GbE PHY Data Interfaces 118
- Serial Data Interface 121
- Register Interface Signals 123
- Addr Bit R/W Name Description 124
- 1G/10 GbE GMII PCS Registers 127
- Cntl & 131
- Editing a 1G/10GbE MIF File 132
- Creating a 1G/10GbE Design 133
- Simulation Support 139
- TimeQuest Timing Constraints 139
- WAN Wide Area Network 140
- XAUI PHY IP Core 141
- XAUI PHY Release Information 142
- Stratix V Devices 143
- Parameterizing the XAUI PHY 143
- XAUI PHY General Parameters 144
- Name Value Description 145
- XAUI PHY Analog Parameters 146
- Advanced Options Parameters 148
- XAUI PHY Configurations 149
- XAUI PHY Ports 150
- XAUI PHY Data Interfaces 151
- SDR XGMII TX Interface 152
- SDR XGMII RX Interface 153
- XAUI Hard IP Core 154
- Hard PCS 154
- Soft PCS 154
- Name Direction Description 157
- Interlaken PHY IP Core 168
- Parameter Value Description 170
- Interlaken PHY Interfaces 173
- Interlaken PHY PLL Interface 181
- Preset C 198
- PHY for PCIe (PIPE) Clocks 201
- Signal Name 202
- Direction Signal Name 202
- PHY IP Core for PCI Express 204
- Hard PCS and PMA 204
- Phase 2 (Optional) 210
- Phase 3 (Optional) 211
- Custom PHY IP Core 214
- Parameterizing the Custom PHY 216
- Word Alignment Parameters 220
- Rate Match FIFO Parameters 222
- Byte Order Parameters 224
- Analog Parameters 229
- Presets for Ethernet 229
- Interfaces 232
- Configuration Bus Used Bits 234
- Clock Interface 236
- Optional Status Interface 237
- Custom PHY PCS and PMA 241
- Custom PHY IP Core Registers 242
- Reset Controls –Manual Mode 243
- Custom PCS 245
- Dynamic Reconfiguration 246
- Low Latency PHY IP Core 248
- General Options Parameters 251
- Additional Options Parameters 254
- TX PLL (0–3) 258
- (Refer to 258
- Channel Interface 259
- Low Latency PHY Interfaces 260
- PMA and Light-Weight PCS 264
- Data Rate (Mbps) 270
- TX_tc lock_output 273
- PDI O >R X_ deser 273
- Serial Data Rate (Mbps) 277
- Single-Width Double-Width 277
- 8-Bit 16-Bit 16-Bit 32-Bit 277
- TX Data Word Description 285
- RX Data Word Description 286
- Deterministic PHY IP Core 291
- Parameter Presets 301
- Name Range Description 302
- Parameter Range Description 304
- PATTERN POLYNOMIAL 323
- PCS-PMA Width 323
- 8-Bit 10-Bit 16-Bit 20-Bit 323
- 10G PCS Pattern Generators 340
- Native PHY Common Interfaces 345
- Standard PCS Interface Ports 351
- Name Dir Synchronous to 353
- Description 353
- 10G PCS Interface 356
- 10G PCS Interface Ports 357
- ×6/×N Bonded Clocking 367
- Transceiver Bank 368
- Slew Rate Settings 374
- General Parameters 378
- PMA Parameters 379
- TX PMA Parameters 380
- TX PLL Parameters 381
- RX PMA Parameters 383
- Standard PCS Parameters 385
- Phase Compensation FIFO 387
- Rate Match FIFO 390
- Overview 484
- Cyclone Device Family Support 485
- Altera V-Series FPGA 520
- Utilization 522
- Embedded 529
- Controller 529
- Offset Cancellation 530
- Duty Cycle Calibration 530
- EyeQ Usage Example 536
- Turning on Triggered DFE Mode 540
- Channel Reconfiguration 550
- PLL Reconfiguration 550
- MIF Generation 554
- MIF Format 555
- Reduced MIF Creation 559
- Register-Based Read 560
- Direct Write Reconfiguration 561
- Reconfiguration 565
- Loopback Modes 575
- Transceiver 576
- Transceiver PHY Instance 579
- Transceiver PHY 579
- Reset Controller 579
- Transceiver PLL Parameters 592
- Transceiver PLL Signals 593
- XCVR_IO_PIN_TERMINATION 596
- XCVR_REFCLK_PIN_TERMINATION 597
- XCVR_TX_SLEW_RATE_CTRL 597
- XCVR_VCCR_ VCCT_VOLTAGE 598
- CDR_BANDWIDTH_PRESET 598
- PLL_BANDWIDTH_PRESET 599
- XCVR_RX_DC_GAIN 599
- XCVR_ANALOG_SETTINGS_PROTOCOL 599
- XCVR_RX_COMMON_MODE_VOLTAGE 600
- XCVR_RX_SD_ENABLE 601
- XCVR_RX_SD_OFF 601
- XCVR_RX_SD_ON 602
- XCVR_RX_SD_THRESHOLD 602
- XCVR_TX_COMMON_MODE_VOLTAGE 603
- XCVR_TX_PRE_EMP_1ST_POST_TAP 603
- XCVR_TX_RX_DET_ENABLE 603
- XCVR_TX_RX_DET_MODE 604
- XCVR_TX_VOD 604
- XCVR_TX_VOD_PRE_EMP_CTRL_SRC 604
- XCVR_RX_BYPASS_EQ_STAGES_234 606
- XCVR_VCCA_VOLTAGE 607
- XCVR_VCCR_VCCT_VOLTAGE 608
- XCVR_TX_PRE_EMP_PRE_TAP_USER 615
- XCVR_TX_PRE_EMP_2ND_POST_TAP 616
- XCVR_TX_PRE_EMP_INV_2ND_TAP 616
- XCVR_TX_PRE_EMP_INV_PRE_TAP 617
- XCVR_TX_PRE_EMP_PRE_TAP 617
- XCVR_TX_RX_DET_OUTPUT_SEL 618
- XCVR_GT_IO_PIN_TERMINATION 628
- XCVR_GT_RX_DC_GAIN 635
- XCVR_GT_RX_CTLE 636
- XCVR_GT_TX_PRE_EMP_ PRE_TAP 638
- XCVR_GT_TX_VOD_MAIN_TAP 638
- Transceivers 648
- 2013.12.20 650
- Stratix IV GX Devices 651
- Parameter Name 653
- Comments 653
- Custom PHY Width 659
- Chapter Document 661
- Changes Made 661
- Date Document 676
- How to Contact Altera 702
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