Altera Transceiver PHY IP Core Manual de usuario

Altera Transceiver PHY IP Core UserGuideSubscribeSend FeedbackUG-010802015.01.12101 Innovation DriveSan Jose, CA 95134www.altera.com

Enabling the Standard PCS PRBS Verifier Using Streamer-Based Reconfiguration...16-46Enabling the Standard PCS PRBS Generator Using Streamer-Base

WordAddrBit R/W Name Description13:8 RO LD coefficientstatus[5:0]Status report register for the contents of the second, 16-bitword of the training fra

WordAddrBit R/W Name Description23 ROorRWLP PresetCoefficientsWhen set to 1, The local device TX coefficients are set to astate where equalization is

WordAddrBit R/W Name Description0xD55:0 R LT VOD setting Stores the most recent VOD setting that LT specified using theTransceiver Reconfiguration Con

WordAddrBit R/W Name Description20:16 RW LT VPOST ovrd Override value for the VPOSTRULE parameter. Whenenabled, this value substitutes for the VPOSTRU

Addr Bit Access Name Description0x64 [31:0] RW pma_rx_set_locktodataWhen set, programs the RX CDR PLL to lock to theincoming data.0x65 [31:0] RW pma_r

Table 4-22: PCS RegistersAddr Bit AccessName Description0x80 31:0 RW Indirect_addr Because the PHY implements a single channel, thisregister must rema

7. Create a MIF for each configuration and associate each MIF with a ROM created in Step 6. Forexample, create a MIF for 1G with 1588 , a MIF for 10G

Example 4-1: Edits to a MIF to Remove PMA SettingsUG-010802015.01.19Editing a 10GBASE-KR MIF File4-51Backplane Ethernet 10GBASE-KR PHY IP Core with Ea

Design ExampleFigure 4-12: PHY-Only Design Example with Two Backplane Ethernet and Two Line-Side (1G/10G)Ethernet ChannelsNative Hard PHYSTDRX PCSTX P

SDC Timing ConstraintsThe SDC timing constraints and approaches to identify false paths listed for Stratix V Native PHY IPapply to all other transceiv

Migrating from Stratix IV to Stratix V Devices Overview...20-1Differences in Dynamic Reconfiguration for Stratix IV and St

1G/10 Gbps Ethernet PHY IP Core52015.01.19UG-01080SubscribeSend FeedbackThe 1G/10 Gbps Ethernet PHY MegaCore® (1G/10GbE) function allows you to instan

Figure 5-1: Level Modules of the 1G/10GbE PHY MegaCore FunctionAltera Device with 10.3125+ Gbps Serial Transceivers1G/10Gb Ethernet PHY MegaCore Funct

Item DescriptionProduct ID 0106Vendor ID 6AF7Device Family SupportIP cores provide either final or preliminary support for target Altera device famili

PHY Module Options ALMs M20K Memory Logic Registers1GbE/10GbE - 1GbE onlywith Sequencer400 0 7001GbE/10GbE - 1GbE/10GbEwith 15881000 4 20001GbE/10GbE

Parameter Name Options DescriptionEnable IEEE 1588 Precision TimeProtocolOn/Off When you turn this option On, the core includesa module in the PCS to

Parameter Name Options DescriptionLink fail inhibit time for 10GbEthernet504 ms Specifies the time before link_status is set toFAIL or OK. A link fail

1G/10GbE PHY InterfacesFigure 5-2: 1G/10GbE PHY Top-Level Signalsxgmii_tx_dc[71:0]xgmii_tx_clkxgmii_rx_dc[71:0]xgmii_rx_clkgmii_tx_d[7:0]gmii_rx_d[7:0

1G/10GbE PHY Clock and Reset InterfacesThis topic illustrates the 1G/10GbE PHY clock and reset connectivity and describes the clock and resetsignals.U

Table 5-6: Clock and Reset SignalsSignal Name Direction Descriptionrx_recovered_clk Output The RX clock which is recovered from the receiveddata. You

Signal Name Direction Descriptionxgmii_tx_dc[71:0]Input XGMII data and control for 8 lanes. Each laneconsists of 8 bits of data and 1 bit of control.x

Introduction to the Protocol-Specific andNative Transceiver PHYs12015.01.19UG-01080SubscribeSend FeedbackThe Arria V, Cyclone V, and Stratix V support

Signal Name Direction Descriptionled_disp_errOutput Disparity error signal indicating a 10-bit runningdisparity error. Asserted for one rx_clkout_1gcy

Table 5-9: RX XGMII Mapping to Standard SDR XGMII InterfaceThe 72-bit RX XGMII data bus format is different from the standard SDR XGMII interface. Thi

Signal Name Direction Descriptionrx_hi_ber Output Asserted by the BER monitor block to indicate aSync Header high bit error rate greater than 10-4.pll

Signal Name Direction Descriptionrx_latency_adj_1g[21:0] Output When you enable 1588, this signal outputs the realtime latency in GMII clock cycles (1

Signal Name Direction Descriptionmgmt_write Input Write signal. Active high.mgmt_read Input Read signal. Active high.mgmt_waitrequest Output When asse

Addr Bit R/W Name Description0xB1 0 RO SEQ Link Ready When asserted, the sequencer is indicating thatthe link is ready.Related InformationAvalon Inter

Table 5-15: PMA Registers - TX and RX Serial Data InterfaceThe following PMA registers allow you to customize the TX and RX serial data interfaceAddre

Addr Bit AccessName Description0x821 RO HI_BER High BER status. When set to 1, the PCS is reporting ahigh BER. When set to 0, the PCS is not reporting

Addr Bit R/W Name Description0x945RW FD Full-duplex mode enable for the local device. Set to 1for full-duplex support.6 RW HD Half-duplex mode enable

Addr Bit R/W Name Description0x955R FD Full-duplex mode enable for the link partner. This bitshould always be 1 because only full duplex issupported.6

Figure 1-1: Transceiver PHY Top-Level ModulesTo MACTo HSSI PinsTransceiver PHY PMA PCSCustomized functionality for:10GBASE-R10GBASE-KR1G/10GBASE-RXAUI

Address Bit R/W Name Description0xA80 RW tx_invpolarity When set to 1, the TX interface inverts the polarity of theTX data. Inverted TX data is input

Figure 5-4: Block Diagram for Reconfiguration Example1G/10GbEthernetMACBackplane-KR or 1G/10Gb Ethernet PHY MegaCore FunctionBackplane-KR or 1G/10Gb E

• Channel number—specifies the requested channel• Mode—specifies 1G or 10G mode for the corresponding channel2. Select a channel for reconfiguration a

Example 5-1: Edits to a MIF to Remove PMA SettingsCreating a 1G/10GbE DesignHere are the steps you must take to create a 1G/10GbE design using this PH

8. Generate a fractional PLL to create the 156.25 MHz XGMII clock from the 10G reference clock.9. Instantiate the PHY in your design based on the requ

Signal Name Direction Descriptiontap_to_upd[2:0] Output Specifies the TX equalization tap to update tooptimize signal quality. The following encodings

Signal Name Direction Descriptionmode_1g_10gbar Input This signal indicates the requested mode for thechannel. A 1 indicates 1G mode and a 0 indicates

Figure 5-5: Level Modules of the 1G/10GbE PHY MegaCore FunctionAltera Device with 10.3125+ Gbps Serial Transceivers1G/10Gb Ethernet PHY MegaCore Funct

Design ExampleFigure 5-6: PHY-Only Design Example with Two Backplane Ethernet and Two Line-Side (1G/10G)Ethernet ChannelsNative Hard PHYSTDRX PCSTX PM

Simulation SupportThe 1G/10GbE and 10GBASE-KR PHY IP core supports the following Altera-supported simulators forthis Quartus II software release:• Mod

Figure 1-2: Stratix V Transceiver Native PHY IP CorePLLsPMAaltera _xcvr_native_ <dev>Transceiver Native PHYTransceiverReconfigurationControllerR

Acronym DefinitionPMA Physical Medium Attachment.PMD Physical Medium Dependent.SGMII Serial Gigabit Media Independent Interface.WAN Wide Area Network.

XAUI PHY IP Core62015.01.19UG-01080SubscribeSend FeedbackThe Altera XAUI PHY IP Core implements the IEEE 802.3 Clause 48 specification to extend theop

XAUI PHY Release InformationThis section provides information about this release of the XAUI PHY IP Core.Table 6-1: XAUI Release InformationItem Descr

Device Family SupportStratix IV GX and GT devices-Soft or hard PCS andPMAFinalStratix V devices-Soft PCS + PMA FinalOther device families No supportDX

a. General Parametersb. Analog Parametersc. Advanced Options Parameters5. Click Finish to generate your customized XAUI PHY IP Core.XAUI PHY General P

Name Value DescriptionXAUI interface typeHard XAUISoft XAUIDDR XAUIIThe following 3 interface types are available:• Hard XAUI–Implements the PCS andPM

Example 6-1 shows how to remove the restriction on logical lane 0 channel assignment in Stratix Vdevices by redefining the pma_bonding_master paramete

Name Value DescriptionPre-emphasis pre-tap setting 0–7 Sets the amount of pre-emphasis on theTX buffer. Available for Stratix IV.Invert the pre-emphas

Name Value DescriptionReceiver static equalizer setting 0–15 This option sets the equalizer controlsettings. The equalizer uses a pass bandfilter. Spe

XAUI PHY ConfigurationsThis section describes configurations of the IP core.The following figure illustrates one configuration of the XAUI IP Core. As

Datapaths Stratix V Arria V Arria V GZ Cyclone VStandard:This datapath provides acomplete PCS and PMA forthe TX and RX channels. Youcan customize the

XAUI PHY PortsThis section describes the ports for the IP core.Figure 6-3 illustrates the top-level signals of the XAUI PHY IP Core for the hard IP im

The following figure illustrates the top-level signals of the XAUI PHY IP Core for the soft IP implementa‐tion for both the single and DDR rates.Figur

For the DDR XAUI variant, the start of control character (0xFB) is aligned to either byte 0 or byte 5.Figure 6-6: Byte 0 Start of Frame Transmission E

Table 6-7: SDR TX XGMII InterfaceSignal Name Direction Descriptionxgmii_tx_dc[71:0] OutputContains 4 lanes of data and control for XGMII. Each lanecon

Figure 6-8: Clock Inputs and Outputs for IP Core with Hard PCSXAUI Hard IP Core4 x 3.125 Gbps serialHard PCStx_coreclkrx_cruclkpll_inclkcoreclkoutxgmi

Signal Name Direction Descriptionxgmii_tx_clk Input The XGMII TX clock which runs at 156.25 MHz.Connect xgmii_tx_clk to xgmii_rx_clk to guarantee this

XAUI PHY Optional PMA Control and Status InterfaceYou can access the state of the optional PMA control and status signals available in the soft IP imp

neous value of a signal to ensure correct functioning of the XAUI PHY. In such cases, you can include therequired signal in the top-level module of yo

Name Direction Descriptionrx_errdetect[7:0] Output Transceiver 8B/10B code group violation or disparityerror indicator. If either signal is asserted,

Table 6-14: Avalon-MM PHY Management InterfaceSignal Name Direction Descriptionphy_mgmt_clk InputAvalon-MM clock input.There is no frequency restricti

PCSThe PCS implements part of the physical layer specification for networking protocols. Depending uponthe protocol that you choose, the PCS may inclu

Word Addr Bits R/W Register Name Description0x022 [31:0] R pma_tx_pll_is_locked Bit[P] indicates that the TX CMU PLL (P) islocked to the input referen

Word Addr Bits R/W Register Name Description0x061 [31:0] RW phy_serial_loopback Writing a 1 to channel <n> puts channel<n> in serial loopb

Word Addr Bits R/W Register Name Description0x084[31:16] - Reserved -[15:8]Rpatterndetect[7:0]When asserted, indicates that theprogrammed word alignme

Word Addr Bits R/W Register Name Description0x086[31:8] - Reserved -[7:4]R,stickyphase_comp_fifo_error[3:0]Indicates a RX phase compensation FIFOoverf

Word Addr Bits R/W Register Name Description0x088[31:8] - Reserved -[7:4]R,stickyrmfifofull[3:0]When asserted, indicates that rate matchFIFO is full (

• Transceiver Architecture in Stratix V DevicesXAUI PHY Dynamic Reconfiguration for Arria II GX, Cyclone IV GX,HardCopy IV GX, and Stratix IV GXThe Ar

Example 6-2: Informational Messages for the Transceiver Reconfiguration InterfacePHY IP will require 8 reconfiguration interfaces for connection to th

Table 6-17: Reconfiguration InterfaceSignal Name Direction Descriptionreconfig_to_xcvr [(<n>70)-1:0]Input Reconfiguration signals from the Trans

Interlaken PHY IP Core72015.01.19UG-01080SubscribeSend FeedbackThe Altera Interlaken PHY IP Core implements Interlaken Protocol Specification, Rev 1.2

The Interlaken PCS supports the following framing functions on a per lane basis:• Gearbox• Block synchronization• Metaframe generation and synchroniza

The Transceiver PHY Reset Controller IP Core handles all reset sequencing of the transceiver to enablesuccessful operation. Because the Transceiver PH

Parameterizing the Interlaken PHYThe Interlaken PHY IP Core is available when you select the Arria V GZ or Stratix V devices. Completethe following st

Parameter Value DescriptionMetaframe length inwords5-8191Specifies the number of words in a metaframe. Thedefault value is 2048.Although 5 -8191 words

Parameter Value DescriptionBase data rate1 × Lane rate2 × Lane rate3 × Lane rateThis option allows you to specify a Base data rate tominimize the numb

Click on the appropriate link to specify the analog options for your device:Related Information• Analog Settings for Arria V GZ Devices on page 19-11•

Interlaken PHY Avalon-ST TX InterfaceThis section lists the signals in the Avalon-ST TX interface.Table 7-4: Avalon-ST TX SignalsSignal Name Direction

Signal Name Direction Descriptiontx_parallel_data<n>[65] InputWhen asserted, indicates that tx_parallel_data<n>[63:0] is valid and is read

Signal Name Direction Descriptionmulti-lane configurations, the tx_datain_bp<n>signals must be logically Ored. The latency on thisAvalon-ST inte

Signal Name Direction Descriptionpll_locked Output In multilane Interlaken designs, this signal is thebitwise AND of the individual lane pll_locked si

Signal Name Direction Descriptionrx_parallel_data<n>[64]OutputWhen asserted, indicates that rx_parallel_data<n>[63:0] isvalid. When deasse

Signal Name Direction Descriptionrx_parallel_data<n>[67]Output When asserted, indicates an RX FIFO overflow error.rx_parallel_data<n>[68]O

Figure 1-3: Directory Structure for Generated Files<instance_name> _sim/synopsys - Simulation files for Synopsys simulation tools<project_di

Signal Name Direction Descriptionrx_parallel_data<n>[70]OutputWhen asserted, indicates that the RX frame synchronizationstate machine has found

Signal Name Direction Descriptionrx_dataout_bp<n> InputWhen asserted, enables reading of data from the RX FIFO. Thissignal functions as a read e

Table 7-7: PLL InterfaceSignal Name Direction Descriptionpll_ref_clk InputReference clock for the PHY PLLs. Refer to the Lanerate entry in the Table 7

Interlaken PHY Register Interface and Register DescriptionsThis section describes the register interface and register descriptions.The Avalon-MM PHY m

Table 7-10: Interlaken PHY RegistersWord Addr Bits R/W Register Name DescriptionPMA Common Control and Status Registers0x022 [<p>-1:0] RO pma_tx

Word Addr Bits R/W Register Name DescriptionThe Interlaken PHY IP requires the useof the embedded reset controller toinitiate the correct the reset se

Word Addr Bits R/W Register Name Description0x065 [31:0] RW pma_rx_set_locktoref When set, programs the RX CDR PLL tolock to the reference clock. Bit

Why Transceiver Dynamic ReconfigurationDynamic reconfiguration is necessary to calibrate transceivers to compensate for variations due to PVT.As silic

Signal Name Direction Descriptionreconfig_from_xcvr[(<n>46)-1:0]Output Reconfiguration signals to the Transceiver ReconfigurationController. <

PHY IP Core for PCI Express (PIPE)82015.01.19UG-01080SubscribeSend FeedbackThe Altera PHY IP Core for PCI Express (PIPE) implements physical coding su

File Name Descriptionsv_xcvr_native.sv Defines the transceiver. It includes instantiations ofthe PCS and PMA modules and Avalon-MM PHYmanagement inter

Figure 8-1: Gen3 PCI Express PHY (PIPE) with Hard IP PCS and PMA in Arria V GZ and Stratix V GXDevices PHY IP Core for PCI Express - Gen3Arria V GZ or

• Stratix V Hard IP for PCI Express IP Core User Guide• Transceiver Configurations in Arria V GZ Devices or Transceiver Configurations in Stratix VDev

Table 8-2: PHY IP Core for PCI Express General OptionsName Value DescriptionDevice familyStratix VArria V GZArria V GXArria V GTArria V SXArria V STSu

Name Value DescriptionGen1 and Gen2 PLL typeCMUATXYou can select either the CMU orATX PLL. The CMU PLL has a largerfrequency range than the ATX PLL.Th

• PHY Interface for the PCI Express Architecture PCI Express 3.0PHY for PCIe (PIPE) InterfacesThis section describes interfaces of the PHY IP Core for

For more information about _hw.tcl files, refer to refer to the Component Interface Tcl Reference chapterin volume 1 of the Quartus II Handbook.Relate

Signal Name Direction Descriptiontx_blk_start Input For Gen3, specifies start block byte location for TXdata in the 128-bit block data. Used when thei

Signal Name Direction Descriptionpipe_g3_txdeemph[17:0] InputFor Gen3, selects the transmitter de-emphasis. The18 bits specify the following coefficie

Signal Name Direction Descriptionrx_eidleinfersel[3<n>-1:0] InputWhen asserted high, the electrical idle state isinferred instead of being ident

PHY for PCIe (PIPE) Output Data to the PHY MACThis section describes the PIPE output signals. These signals are driven from the PCS to the PHY MAC.Thi

ContentsIntroduction to the Protocol-Specific and Native Transceiver PHYs... 1-1Protocol-Specific Transceiver PHYs...

When you specify multiple .spd files, the ip-make-simscript utility generates a single simulation scriptcontaining all required simulation information

Signal Name Direction Descriptionpipe_rx_data_valid Output For Gen3, this signal is deasserted by the PHY to instructthe MAC to ignore pipe_rxdata for

PHY for PCIe (PIPE) ClocksThis section describes the clock ports.Table 8-6: Clock PortsSignal Name Direction Descriptionpll_ref_clk Input This is the

Add the following command to force Timequest analysis at 62.5 MHz.create_generated_clock -name clk_g1 -source [get_ports {pll_refclk}] \-divide_by 8

Table 8-9: Transceiver Differential Serial InterfaceSignal Name Direction Descriptionrx_serial_data[<n>-1:0] Input Receiver differential serial

Figure 8-5: PCI Express PIPE IP Core Top-Level ModulesSystem InterconnectFabricto EmbeddedControllerto ReconfigurationControllerClocks Tx Data, DatakP

Signal Name Direction Descriptionphy_mgmt_write Input Write signal.phy_mgmt_read Input Read signal.phy_mgmt_waitrequest Output When asserted, indicate

Word Addr Bits R/W Register Name Description0x044[31:0] RW reset_fine_controlYou can use the reset_fine_controlregister to create your own reset seque

Word Addr Bits R/W Register Name Description0x064 [31:0] RW pma_rx_set_locktodata When set, programs the RX CDR PLL tolock to the incoming data. Bit &

Word Addr Bits R/W Register Name Description0x083[31:6] RW Reserved —[5:1] RW tx_bitslipboundary_selectSets the number of bits the TX block needsto sl

Word Addr Bits R/W Register Name Description0x086[31:20]R Reserved —[19:16]R rx_rlvWhen set, indicates a run length violation.From block: Word aligner

Getting Started Overview22015.01.19UG-01080SubscribeSend FeedbackThis chapter provides a general overview of the Altera IP core design flow to help yo

“Section 4.2.3 Link Equalization Procedure for 8.0 GT/s Data Rate” in the PCI Express Base Specification,Rev. 3.0 provides detailed information about

The tuning sequence typically includes the following steps:1. The Endpoint receives the starting presets from the Phase 2 training sets sent by the Ro

some instances you may want to override the specified four-stage link equalization procedure todynamically tune PMA settings. Follow these steps to ov

Table 8-12: Reconfiguration Interface SignalsSignal Name Direction Descriptionreconfig_to_xcvr [<r>70-1:0]Input Reconfiguration signals from the

Custom PHY IP Core92015.01.19UG-01080SubscribeSend FeedbackThe Altera Custom PHY IP Core is a generic PHY that you can customize for use in Arria V, C

Figure 9-1: Custom PHY IP CoreDeterministic Latency PHY IP CoreArria V, Cyclone V, or Stratix V FPGAPCS:Phase Comp FIFOsByte Serializer/Deserializer8B

Table 9-2: Custom PHY IP Core Performance and Resource Utilization—Stratix V GT DeviceChannels Combinational ALUTs Logic Registers (Bits)1 142 1544 24

Name Value DescriptionBonding modeNon-bonded or x1Bonded or xNfb_compensationSelect Non-bonded or x1 to use separate clocksources for each channel. (T

Name Value DescriptionPCS-PMA interface width 8, 10, 16, 20 The PCS-PMA interface width depends on theFPGA fabric transceiver interface width and whet

Name Value DescriptionBase data rate1 × Data rate2 × Data rate4 × Data rateThe base data rate is the frequency of the clock inputto the PLL. Select a

Related Information• Altera• Altera Licensing• Altera Software Installation and LicensingDesign FlowsThis section describes how to parameterize Altera

Name Value DescriptionEnable embedded resetcontrolOn/Off When On, the automatic reset controller initiates thereset sequence for the transceiver. When

Table 9-5: Word Aligner OptionsName Value DescriptionWord alignment modeManualIn this mode you enable the word alignmentfunction by asserting rx_enapa

Name Value DescriptionEnable run length violationcheckingOn/Off If you turn this option on, you can specify therun length which is the maximum legalnu

reference clock frequency is greater than the local receiver reference clock frequency. It inserts SKPsymbols or ordered-sets when the local receiver

Table 9-8: 8B/10B OptionsName Value DescriptionEnable 8B/10B decoder/encoder On/Off Enable this option if your applicationrequires 8B/10B encoding and

Table 9-9: Byte Order OptionsName Value DescriptionEnable byte ordering block On/Off Turn this option on if your application usesserialization to crea

Name Value DescriptionEnable byte ordering blockmanual controlOn/Off Turn this option on to choose manual controlof byte ordering. This option creates

Name Value DescriptionByte ordering pad pattern 00000000 Specifies the pad pattern that is inserted toalign the SOP. Enter the following size padpatte

Name Value DescriptionNumber of reference clocks 1-5 Specifies the number of input referenceclocks. More than one reference clock may berequired if yo

Name Value DescriptionEnable channel interface On/Off Turn this option on to enable PLL anddatapath dynamic reconfiguration. When youselect this optio

MegaWizard Plug-In Manager FlowThis section describes how to specify parameters and simulate your IP core with the MegaWizard Plug-InManager.The MegaW

Parameter Name GIGE-1.25 Gbps GIGE-2.50 GbpsPCS-PMA Interface Width 10 10Data rate 1250 Mbps 3125 MbpsInput clock frequency 62.5 MHz 62.5 MHzEnable TX

Parameter Name GIGE-1.25 Gbps GIGE-2.50 GbpsEnable 8B/10B decoder/encoder On OnEnable manual disparity control Off OffCreate optional 8B/10B status po

InterfacesFigure 9-2: Custom PHY Top-Level SignalsThe variables in Figure 9–2 represent the following parameters:• <n>—The number of lanes• <

Table 9-12: Avalon-ST TX Interface SignalsSignal Name Direction Descriptiontx_parallel_data[(<n>43:0]Input This is TX parallel data driven from

Table 9-13: Location of Valid Data Words for tx_parallel_data for Various FPGA Fabric to PCSParameterizationsThe following table shows the valid 11-bi

Table 9-14: Avalon-ST RX Interface SignalsThese signals are driven from the PCS to the MAC. This is an Avalon source interface.Signal Name Direction D

Signal Name Direction Descriptionrx_clkout[< n >-1:0] Output This is the clock for the RX parallel data sourceinterface.rx_datak[< n >(<

Table 9-17: Clock SignalsSignal Name Direction Descriptionpll_ref_clk Input Reference clock for the PHY PLLs. Frequencyrange is 50-700 MHz.rx_coreclki

Signal Name Direction Signal Namerx_errdetect[<n>(<w>/<s>)-1:0] Output When asserted, indicates that areceived 10-bit code group has

Signal Name Direction Signal Namerx_rmfifodatainserted[<n>-1:0] Output When asserted, indicates that the RXrate match block inserted an ||R||col

Note: The Finish button may be unavailable until all parameterization errors listed in the messageswindow are corrected.8. Click Yes if you are prompt

Signal Name Direction Descriptiontx_cal_busy[<n>-1:0] Output When asserted, indicates that the initial TXcalibration is in progress. It is also

Figure 9-4: Custom PHY IP CoreSystem InterconnectFabricto EmbeddedControllerCustom PHY PCS and PMACustom PHY IP CoreResetsStatusControlSAvalon-MMContr

Signal Name Direction Descriptionphy_mgmt_readdata[31:0] Output Output data.phy_mgmt_write Input Write signal.phy_mgmt_read Input Read signal.phy_mgmt

WordAddrBits R/W Register Name Description0x042 [1:0]W reset_control (write) Writing a 1 to bit 0 initiates a TX digitalreset using the reset controll

WordAddrBits R/W Register Name Description[2] RW reset_rx_analog Writing a 1 causes the internal RX analogreset signal to be asserted, resetting theRX

Custom PCSTable 9-25: Custom PCSWordAddrBits R/W Register Name Description0x080 [31:0] RW Lane or group number Specifies lane or group number forindir

WordAddrBits R/W Register Name Description0x085[3] RW rx_bitslip Every time this register transitions from 0to 1, the RX data slips a single bit.To bl

Example 9-1: Informational Messages for the Transceiver Reconfiguration InterfacePHY IP will require 2 reconfiguration interfaces for connection to th

Low Latency PHY IP Core102015.01.19UG-01080SubscribeSend FeedbackThe Altera Low Latency PHY IP Core receives and transmits differential serial data, r

Device Family SupportIP cores provide either final or preliminary support for target Altera device families. These terms have thefollowing definitions

10GBASE-R PHY IP Core32015.01.19UG-01080SubscribeSend FeedbackThe Altera 10GBASE-R PHY IP Core implements the functionality described in IEEE Standard

Implementa‐tionNumber ofLanesSerializationFactorWorst-CaseFrequencyCombinationalALUTsDedicatedRegistersMemory Bits6 Gbps (8Gbpsdatapath)1 32 or 40 607

• General Options Parameters on page 10-4• Additional Options Parameters on page 10-7• PLL Reconfiguration Parameters on page 10-10• Low Latency PHY A

Name Value DescriptionBonding mode ×N fb_compensationSelect ×N to use the same clock source forup to 6 channels in a single transceiver bank,resulting

Name Value DescriptionData rate DevicedependentSpecifies the data rate in Mbps. Refer toStratix V Device Datasheet for the data rateranges of datapath

FPGA Fabric -Transceiver InterfaceWidthPCS-PMA Interface Widthtx_clkout and rx_clkout frequencyStandard Datapath10G Datapath50 — 40 data rate/50 (6)64

The following table describes the options available on the Additional Options tab:Table 10-5: Additional OptionsName Value DescriptionEnable tx_corecl

Name Value DescriptionEnable TX bitslip On/Off The bit slip feature allows you to slip thetransmitter side bits before they are sent to thegearbox. Th

Name Value DescriptionAvalon data interfaces On/Off When you turn this option On, the order ofsymbols is changed. This option is typicallyrequired if

Name Value DescriptionNumber of TX PLLs 1–4 Specifies the number of TX PLLs that can beused to dynamically reconfigure channels torun at multiple data

TX PLL (0–3)(Refer to Low Latency PHY General Options for a detailed explanation of these parameters.)Reference clock frequency Variable Specifies the

To make the most effective use of this soft PCS and PMA configuration for Stratix IV GT devices, you cangroup up to four channels in a single quad and

Related InformationAnalog Parameters Set Using QSF Assignments on page 19-1Low Latency PHY InterfacesThe following figure illustrates the top-level si

Table 10-7: Avalon-ST interface Signal Name Direction Descriptiontx_parallel_data[<n><w>-1:0]Input This is TX parallel data driven from t

Optional Status InterfaceThe following table describes the signals that comprise the optional status interface:Table 10-9: Optional Status Interface S

Signal Name Direction Descriptionpll_ref_clkInput Reference clock for the PHY PLLs. Thefrequency range is 60–700 MHz.Optional Reset Control and Status

Register Interface and Register DescriptionsThe Avalon-MM PHY management interface provides access to the Low Latency PHY PCS and PMAregisters that co

Signal Name Direction Descriptionphy_mgmt_writedata[31:0]Input Input data.phy_mgmt_readdata[31:0]Output Output data.phy_mgmt_writeInput Write signal.p

Word Addr Bits R/W Register Name DescriptionReset Control Registers–Automatic Reset Controller0x063 [31:0] Rpma_rx_signaldetectWhen channel <n>

Controller IP Cores. Doing so causes a Fitter error. For more information, refer to Transceiver Reconfigu‐ration Controller to PHY IP Connectivity.The

Related InformationSDC Timing Constraints of Stratix V Native PHY on page 12-74This section describes SDC examples and approaches to identify false ti

Deterministic Latency PHY IP Core112015.01.19UG-01080SubscribeSend FeedbackDeterministic latency enables accurate delay measurements and known timing

Figure 3-3: 10GBASE-R PHY IP Core In Arria V GT DevicesTransceiverReconfiguration ControllerDataWiringSoft PCSTX PMAPMARX PMA & CDRCMUPLLResetCont

Figure 11-1: Deterministic Latency PHY IP CoreDeterministic Latency PHY IP CoreArria V, Cyclone V, or Stratix V FPGAPCS:Phase Comp FIFOsByte Serialize

Data Rate (Mbps)Base Data Rate (Mbps) Clock Divider2457.6 4915.2 23072.0 6144.0 24915.2 4915.2 16144.0 6144.0 1Note: You can use PMA Direct mode in th

Figure 11-2: Achieving Deterministic Latency for the TX and RX DatapathsThe TX and RX Phase Compensation FIFOs always operate in register mode.TX Data

Example 11-1: For RERX _latency_ RE = <R X PCS latency in parallel clock cycles > +(<RX PMA latency in UI > + < TX_latenc

Example 11-4: Total Delay UncertaintyRound trip delay estimates are subject to process, voltage, and temperature (PVT) variation.tRXCL K _P hase_detec

PCS Datapath Width RX PhaseComp FIFOByteOrderingDeserial‐izer8B/10B WordAligner (10)(9)Total RX ParallelClock Cycles (9)(10)16 bits 1.0 1.0 1.0 1.0 5.

Parameterizing the Deterministic Latency PHYThis section provides a list of steps on how to configure Deterministic Latency PHY1. Under Tools > IP

Name Value DescriptionData rate Device Dependent If you select a data rate that is not supported by theconfiguration you have specified, the MegaWizar

Serial Data Rate (Mbps)Channel Width (FPGA-PCS Fabric)Single-Width Double-Width8-Bit 16-Bit 16-Bit 32-Bit1228.8 Yes Yes Yes Yes2457.6 No Yes Yes Yes30

Name Value DescriptionWord alignment modeDeterministiclatency statemachineDeterministic latency state machine–In this mode,the RX word aligner automat

Figure 3-4: 10GBASE-R PHY IP Core In Arria V GZ DevicesDataWiringPLD-PCS & Duplex PCS PCS-PMAPCSTX PMAPMARX PMA & CDRGenericPLLResetController

Name Value DescriptionWord alignment mode Manual Manual–In this mode, the RX word aligner parses theincoming data stream for a specific alignmentchara

Name Value DescriptionEnable embedded resetcontrollerOn/ Off When you turn this option On, the embedded resetcontroller handles reset of the TX and RX

Name Value DescriptionNumber of reference clocks 1-5 Specifies the number of input reference clocks.More than one reference clock may be required ifyo

Name Value DescriptionEnable channel interface On/Off Turn this option on to enable PLL and datapathdynamic reconfiguration. When you select thisoptio

Figure 11-3: Deterministic Latency PHY Top-Level Signalstx_parallel_data[< n><w>-1>:0]tx_clkout[<n>-1:0]tx_datak[(<n>(<w

Table 11-9: Avalon-ST TX InterfaceThe following table describes the signals in the Avalon-ST input interface. These signals are driven from the MACto

Table 11-11: Avalon-ST RX InterfaceThe following table describes the signals in the Avalon-ST output interface. These signals are driven from the PCSt

RX Data Word Descriptionrx_parallel_data[10] Word Aligner / synchronization statusrx_parallel_data[11] Disparity errorrx_parallel_data[12] Pattern det

Optional TX and RX Status Interface for Deterministic Latency PHYThis section describes the optional TX and RX status interface settings for the Deter

Signal Name Direction Signal Namerx_is_lockedtoref [(<n>(<d>/<s>)-1:0]Output Asserted when the receiver CDR is locked tothe input re

Figure 3-5: 10GBASE-R PHY IP Core In Stratix V DevicesDataWiringPLD-PCS & Duplex PCS PCS-PMAPCSTX PMAPMARX PMA & CDRGenericPLLResetControllerP

Signal Name Direction Descriptionrx_cal_busy [<n>-1:0] Output When asserted, indicates that theinitial RX calibration is in progress. Itis also

Figure 11-4: Deterministic Latency PHY IP CoreSystem InterconnectFabricSystem InterconnectFabricDeterministic PHY PCS and PMADeterministic PHY IP Cor

Signal Name Direction Descriptionphy_mgmt_waitrequest Output When asserted, indicates that the Avalon-MM slaveinterface is unable to respond to a read

Word Addr Bits R/W Register Name Description0x044[31:0]RW reset_fine_control You can use the reset_fine_control register to create your ownreset seque

Word Addr Bits R/W Register Name Description0x067 [31:0] RO pma_rx_is_lockedtoref When asserted, indicates that the RXCDR PLL is locked to the referen

Word Addr Bits R/W Register Name Description0x085[31:4] RW pcs8g_rx_wa_control Reserved.[3] RW rx_bitslip Every time this register transitionsfrom 0 t

Table 11-19: Reconfiguration InterfaceThis table lists the signals in the reconfiguration interface. This interface uses the Avalon-MM PHY Managementi

Figure 11-5: Channel Placement and Available Channels in Arria V DevicesGXB_R0GXB_R1GXB_L0GXB_L1GXB_R2GXB_L2Devices AvailableNumber of Channels Per Ba

Related InformationSDC Timing Constraints of Stratix V Native PHY on page 12-74This section describes SDC examples and approaches to identify false ti

Stratix V Transceiver Native PHY IP Core122015.01.19UG-01080SubscribeSend FeedbackThe Stratix V Transceiver Native PHY IP Core provides direct access

Backplane Ethernet 10GBASE-KR PHY IP Core with Early Access FECOption...

Table 3-2: Latency for TX and RX PCS and PMA Stratix V DevicesPCS (Parallel Clock Cycles)PMA (UI)32-bit PMA Width 40-bit PMA WidthMinimum Maximum Mini

Figure 12-1: Stratix V Native Transceiver PHY IP CorePLLsPMAaltera _xcvr_native_ <dev>Transceiver Native PHYTransceiverReconfigurationController

Performance and Resource Utilization for Stratix V Native PHYThis section describes the performance resource utilization for Stratix V native PHY.Beca

Parameterizing the Stratix V Native PHYThis section provides a list of instructions on how to configure the Stratix V Native PHY IP coreComplete the f

Name Range DescriptionNumber of data channels DeviceDependentSpecifies the total number of data channels in eachdirection. From 1-32 channels are supp

PMA Parameters for Stratix V Native PHYThis section describes the PMA parameters for the Stratix V native PHY.Table 12-3: PMA OptionsThe following tab

TX PMA ParametersTable 12-4: TX PMA ParametersThe following table describes the TX PMA options you can specify.For more information about the TX CMU,

Table 12-5: TX PLL ParametersThe following table describes how you can define multiple TX PLLs for your Native PHY. The Native PHY GUIprovides a separ

RX CDR OptionsTable 12-6: RX PMA ParametersThe following table describes the RX CDR options you can specify. For more information about the CDRcircuit

PMA Optional PortsTable 12-7: RX PMA ParametersThe following table describes the optional ports you can include in your IP Core. The QPI interface imp

Parameter Range DescriptionEnable rx_clkslip port On/Off When you turn this option On, the rx_clkslipcontrol input port is enabled. The deserializer s

Device Family SupportArria V ST devices-Soft PCS and Hard PMA FinalArria V GZ FinalStratix IV GT devices–Soft PCS and Hard PMA FinalStratix V devices–

The following tables lists the bits used for all FPGA fabric to PMA interface widths. Regardless of theFPGA Fabric Interface Width selected, all 80 bi

Standard PCS Parameters for the Native PHYThis section shows the complete datapath and clocking for the Standard PCS and defines the parametersavailab

Table 12-11: General and Datapath ParametersThe following table describes the general and datapath options for the Standard PCS.Parameter Range Descri

Phase Compensation FIFOThe phase compensation FIFO assures clean data transfer to and from the FPGA fabric by compensatingfor the clock phase differen

Parameter Range DescriptionEnable RX byte ordering On/Off When you turn this option On, the PCSincludes the byte ordering block.Byte ordering control

Parameter Range DescriptionEnable rx_std_byteorder_ena port On/Off Enables the optional rx_std_byte_order_ena control input port. When this signal isa

Table 12-14: 8B/10B Encoder and Decoder ParametersParameter Range DescriptionEnable TX 8B/10B encoder On/Off When you turn this option On, the PCSincl

When you enable the simplified data interface and enable the rate match FIFO status ports, the rate matchFIFO bits map to the high-order bits of the d

Status Condition Protocol Mapping of Status Flags to RX Data ValueEmptyPHY IP Core for PCIExpress (PIPE)Basic double widthRXD[62:62] = rx_rmfifostatus

Status Condition Protocol Mapping of Status Flags to RX Data ValueDeletionBasic double widthSerial RapidIO double widthRXD[62:62] = rx_rmfifostatus[1:

Table 3-6: 10GBASE-R PHY Performance and Resource Utilization—Arria V GT DeviceChannels ALMs Primary LogicRegistersSecondary LogicRegistersMemory 10K1

Parameter Range DescriptionRX word aligner modebit_slipsync_smmanualSpecifies one of the following 3 modes for theword aligner:• Bit_slip : You can us

Parameter Range DescriptionEnable rx_std_wa_patternalign port On/Off Enables the optional rx_std_wa_patterna-lign control input port. A rising edge on

Parameter Range DescriptionEnable rx_std_bitrev_ena port On/Off When you turn this option On, asserting rx_std_bitrev_ena control port causes the RXda

PRBS VerifierYou can use the PRBS pattern generators for verification or diagnostics. The pattern generator blockssupport the following patterns:• Pse

PCS-PMA Width8-Bit 10-Bit 16-Bit 20-BitPRBS-10XPRBS 15X X X XPRBS 23X X XPRBS 31X X X XUnlike the 10G PRBS verifier, the Standard PRBS verifier uses t

PCS-PMA Width PRBS Patterns PRBS Pattern Select Word Aligner Size Word Aligner Pattern20-bitPRBS 7 3’b000 3’b100 0x0000043040PRBS 23 3’b001 3’b110 0x0

Offset OffsetBits R/W Name Description0xA3 [15:0] R/W Word Aligner Pattern[15:0]Stores the least significant 16 bitsfrom the word aligner pattern assp

10G PCS Parameters for Stratix V Native PHYThis section shows the complete datapath and clocking for the 10G PCS and defines parameters availablein th

Table 12-23: General and Datapath ParametersParameter Range Description10G PCS protocol modebasicinterlakensfisteng_baserteng_1588teng_sdiSpecifies th

Table 12-24: 10G TX FIFO ParametersParameter Range DescriptionTX FIFO ModeInterlakenphase_compregisterSpecifies one of the following 3 modes:• interla

General Option ParametersThis section describes general parameters.This section describes the 10GBASE-R PHY parameters, which you can set using the Me

Parameter Range DescriptionEnable tx_10g_fifo_pfull port On/Off When you turn this option On , the 10GPCS includes the active high tx_10g_fifo_pfull p

Table 12-25: 10G RX FIFO ParametersParameter Range DescriptionRX FIFO ModeInterlakenclk_compphase_compregisterSpecifies one of the following 3 modes:•

Parameter Range DescriptionEnable RX FIFO control word deletion(Interlaken)On/Off When you turn this option On , the rx_control_del parameter enables

Parameter Range DescriptionEnable rx_10g_fifo_rd_en port(Interlaken)On/Off When you turn this option On, the 10GPCS includes the rx_10g_fifo_rd_eninpu

Parameter Range Descriptionteng_tx_framgen_burst_enable On/Off When you turn this option On, theframe generator burst functionality isenabled.Enable t

Table 12-27: Interlaken Frame Synchronizer ParametersParameter Range Descriptionteng_tx_framsync_enable On/Off When you turn this option On, the 10GPC

Parameter Range DescriptionEnable rx_10g_frame_diag_err port On/Off When you turn this option On, the 10GPCS includes the rx_10g_frame_diag_err output

Table 12-29: 10GBASE-R BER Checker ParametersParameter Range DescriptionEnable rx_10g_highber port(10GBASE-R)On/Off When you turn this option On, the

Scrambler and Descrambler ParametersTX scrambler randomizes data to create transitions to create DC-balance and facilitate CDR circuits basedon the x5

Block SynchronizationThe block synchronizer determines the block boundary of a 66-bit word for the 10GBASE-R protocol or a67-bit word for the Interlak

Name Value DescriptionPCS / PMA interface width3240For Stratix V and Arria V GZ devices only:Specifies the data interface width between the 10GPCS and

Parameter Range DescriptionEnable TX data bitslip On/Off When you turn this option On, the TXgearbox operates in bitslip mode.Enable RX data polarity

Test Enable bits. The following table lists the offsets and registers of the pattern generators and verifiersin the 10G PCS.Note: The 10G PRBS generat

Offset Bits R/W Name Description0x135[15:12] R/WSquare Wave PatternSpecifies the number of consecutive 1sand 0s. The following values areavailable: 1,

Offset Bits R/W Name Description0x15E[14] R/WRX PRBS 7 EnableEnables the PRBS-7 polynomial in thereceiver.[13] R/WRX PRBS 23 EnableEnables the PRBS-23

In addition you have the following options:• You can toggle the Data Pattern Select bit switch between two data patterns.• You can change the value of

Figure 12-5: Stratix V Native PHY Common Interfacestx_pll_refclk[<r>-1:0]tx_pma_clkout[<n>-1:0]rx_pma_clkout[<n>-1:0]rx_cdr_refclk[&

Name Direction Descriptionpll_powerdown[ <p> -1:0] Input When asserted, resets the TX PLL. Activehigh, edge sensitive reset signal. By default,t

Name Direction Descriptiontx_parallel_data[ <n> 64-1:0] Input PCS TX parallel data. Used when you enableeither the Standard or 10G datapath. For

Name Direction Descriptiontx_pma_qpipullup Input Control input port for Quick Path Intercon‐nect (QPI) applications. When asserted, thetransmitted pul

Name Direction Descriptionrx_set_locktoref[ <n> -1:0] Input When asserted, programs the RX CDR tomanual lock to reference mode in whichyou contr

Name Value DescriptionEnable embedded reset control On/Off When On, the automatic reset controller initiatesthe reset sequence for the transceiver. Wh

Table 12-39: Signal Definitions for tx_parallel_data with and without 8B/10B EncodingThe following table shows the signals within tx_parallel_data tha

RX Data Word Descriptionrx_parallel_data[14:13] The following encodings are defined:• 2’b00: Normal data• 2’b01: Deletion• 2’b10: Insertion (or Underf

Figure 12-6: Standard PCS Interfacestx_std_clkout[<n>-1:0] rx_std_clkout[<n>-1:0]tx_std_coreclkin[<n>-1:0]rx_std_coreclkin[<n>

Name Dir Synchronous totx_std_coreclkin/rx_std_coreclkinDescriptionrx_std_pcfifo_empty[<n>-1:0]Output Yes RX phase compensation FIFO statusempty

Name Dir Synchronous totx_std_coreclkin/rx_std_coreclkinDescriptionrx_std_polinv[<n>-1:0]Input No Polarity inversion for the 8B/10B decoder,When

Name Dir Synchronous totx_std_coreclkin/rx_std_coreclkinDescriptionrx_std_bitslipboun-darysel[5<n>-1:0]Output No This signal operates when the w

Name Dir Synchronous totx_std_coreclkin/rx_std_coreclkinDescriptionrx_std_prbs_errOutputYesWhen asserted, indicates an error onlyafter the rx_std_prbs

Figure 12-7: Stratix V Native PHY 10G PCS InterfacesClocksFrameGeneratorTX FIFORX FIFOBlockSynchronizerFrameSynchronizerBit-SlipGearboxFeature64B/66BB

Name Direction Descriptiontx_10g_clkout[<n>-1:0]Output TX parallel clock output for the TX PCS.rx_10g_clkout[<n>-1:0]Output RX parallel cl

Name Direction Descriptiontx_10g_control[9<n>-1:0] (continued)• [2]: Inversion signal, must always be set to 1'b0.• [1]: Sync Header, 1 ind

pma_bonding_master to the 10GBASE-R instance name. You must substitute the instance namefrom your design for the instance name shown in quotation mark

Name Direction Descriptiontx_10g_fifo_pfull[<n>-1:0]Output When asserted, indicates that the TX FIFO is partiallyfull. Synchronous to tx_10g_cor

Name Direction Descriptionrx_10g_control[10<n>-1:0]OutputRX control signals for the Interlaken, 10GBASE-R, and Basicprotocols. These are synchro

Name Direction Descriptionrx_10g_control[10<n>-1:0] (continued)Basic mode: 67-bit mode with Block Sync:• [9]: Active-high synchronous status sig

Name Direction Descriptionrx_10g_fifo_full[<n>-1:0]Output Active high RX FIFO full flag. Synchronous to rx_10g_clkout. This signal is pulse-stre

Name Direction Descriptiontx_10g_diag_status[2<n>-1:0]Input For the Interlaken protocol, provides diagnostic statusinformation reflecting the la

Name Direction Descriptionrx_10g_frame_sync_err[<n>-1:0]Output For the Interlaken protocol, asserted to indicate asynchronization Control Word e

Name Direction Descriptionrx_10g_blk_lock[<n>-1:0]Output Active-high status signal that is asserted when blocksynchronizer acquires block lock.

Name Direction Descriptionrx_10g_prbs_errOutput When asserted, indicates an error only after the rx_10g_prbs_done signal has been asserted. This signa

Figure 12-8: x6 and xN Routing of ClocksTransceiver BankTransceiver Bank×N_top Clock Line (1)×6 Clock Lines (1)×6 Clock Lines (1)×N_bottomClock Lin

Bonded clocks allow you to use the same PLL for up to 13 contiguous channels above and below the TXPLL for a total of 27 bonded channels as the follow

Name Value DescriptionReceiver common modevoltageTri-State0.82V1.1vSpecifies the RX common mode voltage.Receiver terminationresistanceOCT_85_OHMSOCT_1

Figure 12-9: Channel Span for xN Bonded Channels131211TransceiverBank 4ATXPLL1098765TransceiverBank 343211TransceiverBank 2Up to 7channelsabove &b

You can use the tx_clkout from any channel to transfer data, control, and status signals between theFPGA fabric and the transceiver channels. Using th

SDC Timing Constraints of Stratix V Native PHYThis section describes SDC examples and approaches to identify false timing paths.The Quartus II softwar

Example 12-2: Using the max_delay Constraint to Identify Asynchronous InputsYou can use the set_max_delay constraint on a given path to create a const

Example 12-5: Overriding Logical Channel 0 Channel Assignment Restrictions in Stratix VDevice for ×6 or ×N BondingIf you are using ×6 or ×N bonding, t

• Protocol declarations take priority over datarate. For example, XAUI has a per-lane datarate of 3.125Gbps, but only a setting of "3" is al

Arria V Transceiver Native PHY IP Core132015.01.19UG-01080SubscribeSend FeedbackThe Arria V Transceiver Native PHY IP Core provides direct access to a

Figure 13-1: Arria Native Transceiver PHY IP CoreCMUPLLsPMAaltera _xcvr_native_av Transceiver Native PHYReconfiguration to XCVRReconfiguration from XC

Performance and Resource UtilizationThis section describes performance and resource utilization for the IP core.Because the Standard PCS and PMA are i

Name Range DescriptionNumber of data channels 1-36 Specifies the total number of data channels in eachdirection.Bonding mode Bonded or xNNon-bondedor

Figure 3-6: 10GBASE-R PHY Top-Level Signalsxgmii_tx_dc<n>[71:0]tx_readyxgmii_tx_clkxgmii_rx_dc<n>[71:0]rx_readyrx_data_ready[<n>-1:0

Table 13-3: PMA Options Parameter Range DescriptionData rate Device Dependent Specifies the data rate. Themaximum data rate is 12.5 Gbps.PMA direct i

Table 13-4: TX PMA ParametersParameter Range DescriptionEnable TX PLL dynamicreconfigurationOn/Off When you turn this option On, you can dynamicallyre

Table 13-5: TX PLL ParametersParameter Range DescriptionPLL type CMU This is the only PLL type available.PLL base data rate DeviceDependentShows the b

RX PMA ParametersNote: For more information about the CDR circuitry, refer to the Receiver PMA Datapath section in theTransceiver Architecture in Arri

The following table lists the best case latency for the most significant bit of a word for the RX deserializerfor the PMA Direct datapath. PMA Direct

FPGA Fabric Interface Width Bus Bits Used10 bits [9:0]16 bits {[17:10], [7:0]}20 bits [19:0]40 bits [39:0]64 bits {[77:70], [67:60], [57:50], [47:40],

Note: For more information about the Standard PCS, refer to the PCS Architecture section in theTransceiver Architecture in Arria V Devices.The followi

Phase Compensation FIFOThe phase compensation FIFO assures clean data transfer to and from the FPGA fabric by compensatingfor the clock phase differen

Parameter Range DescriptionEnable rx_std_rmfifo_full portOn/Off When you turn this option On, the rate match FIFOoutputs a FIFO full status flag.Relat

Parameter Range DescriptionByte order pattern(hex)User-specified 8-10 bit patternSpecifies the search pattern for the byte ordering block.Byte order p

Signal Name Direction Descriptionxgmii_tx_dc_[<n>71:0] Input Contains 8 lanes of data and control forXGMII. Each lane consists of 8 bits of data

Table 13-13: Byte Serializer and Deserializer ParametersParameter Range DescriptionEnable TX byte serializer On/Off When you turn this option On, the

Table 13-15: Rate Match FIFO ParametersParameter Range DescriptionEnable RX rate matchFIFOOn/Off When you turn this option On, the PCS includes a FIFO

Table 13-16: Status Flag Mappings for Simplified Native PHY InterfaceStatus Condition Protocol Mapping of Status Flags to RX Data ValueFullPHY IP Core

Status Condition Protocol Mapping of Status Flags to RX Data ValueInsertionBasic double widthSerial RapidIO double widthRXD[62:62] = rx_rmfifostatus[1

Table 13-17: Word Aligner and BitSlip Parameters Parameter Range DescriptionEnable TX bit slip On/Off When you turn this option On, the PCSincludes th

Parameter Range DescriptionNumber of invalid words to losesync1–256 Specifies the number of invalid data codes ordisparity errors that must be receive

Table 13-18: Bit Reversal and Polarity Inversion Parameters Parameter Range DescriptionEnable TX bit reversal On/Off When you turn this option On, the

Parameter Range DescriptionEnable tx_std_polinv port On/Off When you turn this option On, the tx_std_polinv input is enabled. You canuse this control

InterfacesThe Native PHY includes several interfaces that are common to all parameterizations.The Native PHY allows you to enable ports, even for disa

Table 13-19: Native PHY Common Interfaces Name Direction DescriptionClock Inputs and Output Signalstx_pll_refclk[<r>-1:0]Input The reference clo

1G/10GbE Control and Status Interfaces...5-12Register Inte

Signal Name Direction Descriptionrx_data_ready [<n>-1:0] Output When asserted, indicates that the PCS issending data to the MAC. Because theread

Name Direction Descriptiontx_analogreset[<n>-1:0]Input When asserted, resets for TX PMA, TXclock generation block, and serializer.Active high, e

Name Direction Descriptiontx_parallel_data[43:0]Input PCS TX parallel data representing 4, 11-bit words. Used when you enable theStandard datapath. Re

Name Direction Descriptionrx_is_lockedtoref[<n>-1:0]Output When asserted, the CDR is locked to theincoming reference clock.rx_clkslip[<n>-

TX Data Word Descriptiontx_parallel_data[9] Force disparity, validates disparity field.tx_parallel_data[10] Specifies the current disparity as follows

RX Data Word Descriptionrx_parallel_data[10] Word alignment / synchronization statusrx_parallel_data[11] Disparity errorrx_parallel_data[12] Pattern d

Figure 13-4: Standard PCS Interfacestx_std_clkout[<n>-1:0] rx_std_clkout[<n>-1:0]tx_std_coreclkin[<n>-1:0]rx_std_coreclkin[<n>

Name Dir Synchronous totx_std_coreclkin/rx_std_coreclkinDescriptionrx_std_pcfifo_empty[<n>-1:0]Output Yes RX phase compensation FIFO statusempty

Name Dir Synchronous totx_std_coreclkin/rx_std_coreclkinDescriptionrx_std_polinv[<n>-1:0]Input No Polarity inversion for the 8B/10B decoder,When

Name Dir Synchronous totx_std_coreclkin/rx_std_coreclkinDescriptionrx_std_bitslipboun-darysel[5<n>-1:0]Output No This signal operates when the w

Name Dir Synchronous totx_std_coreclkin/rx_std_coreclkinDescriptionrx_std_prbs_errOutputYesWhen asserted, indicates an error onlyafter the rx_std_prbs

Signal Name XGMII Signal Name Descriptionxgmii_tx_dc_[44] xgmii_sdr_ctrl[4] Lane 4 controlxgmii_tx_dc_[52:45] xgmii_sdr_data[47:40] Lane 5 dataxgmii_t

Example 13-1: Using the set_false_path Constraint to Identify Asynchronous Inputsset_false_path -through {*8gbitslip*} -to [get_registers *8g_rx_pcs*

For nonbonded clocks, each channel and each TX PLL has a separate dynamic reconfiguration interfaces.The MegaWizard Plug-In Manager provides informati

Arria V GZ Transceiver Native PHY IP Core142015.01.19UG-01080SubscribeSend FeedbackUnlike other PHY IP Cores, the Native PHY IP Core does not include

Figure 14-1: Arria V GZ Native Transceiver PHY IP CorePLLsPMAaltera _xcvr_native_ <dev>Transceiver Native PHYTransceiverReconfigurationControlle

Performance and Resource Utilization for Arria V GZ Native PHYBecause the 10G PCS, Standard PCS, and PMA are implemented in hard logic, the Arria V GZ

Clicking Finish generates your customized Arria V GZ Native PHY IP Core.General Parameters for Arria V GZ Native PHYThis section describes the datapat

Name Range DescriptionBonding modeNon-bonded or x1Bonded or ×6/xNfb_compensationIn Non-bonded or x1 mode, each channel is pairedwith a PLL.If one PLL

PMA Parameters for Arria V GZ Native PHYThis section describes the PMA parameters for the Arria V GZ native PHY.Table 14-3: PMA OptionsThe following t

TX PMA ParametersTable 14-4: TX PMA ParametersThe following table describes the TX PMA options you can specify.For more information about the TX CMU,

TX PLL<n>Table 14-5: TX PLL ParametersThe following table describes how you can define multiple TX PLLs for your Native PHY. The Native PHY GUIp

Table 3-13: 10GBASE-R Status, 1588, and PLL Reference Clock OutputsSignal Name Direction Descriptionrx_block_lock Output Asserted to indicate that the

Parameter Range DescriptionSelected reference clocksource0-4 You can define up to 5 frequencies for the PLLs inyour core. The Reference clock frequenc

Parameter Range DescriptionEnable rx_seriallpbken port On/Off When you turn this option On, the rx_seriallpbkenis an input to the core. When your driv

Parameter Range DescriptionEnable rx_set_lockedtodataand rx_set_locktoref portsOn/Off When you turn this option On, the rx_set_lockedt-data and rx_set

FPGA Fabric Interface Width Arria V GZ Latency in UI80 bits 164The following tables lists the bits used for all FPGA fabric to PMA interface widths. R

Standard PCS Parameters for the Native PHYThis section shows the complete datapath and clocking for the Standard PCS and defines the parametersavailab

Table 14-11: General and Datapath ParametersThe following table describes the general and datapath options for the Standard PCS.Parameter Range Descri

Phase Compensation FIFOThe phase compensation FIFO assures clean data transfer to and from the FPGA fabric by compensatingfor the clock phase differen

Parameter Range DescriptionEnable RX byte ordering On/Off When you turn this option On, the PCSincludes the byte ordering block.Byte ordering control

Parameter Range DescriptionEnable rx_std_byteorder_ena port On/Off Enables the optional rx_std_byte_order_ena control input port. When this signal isa

Table 14-14: 8B/10B Encoder and Decoder ParametersParameter Range DescriptionEnable TX 8B/10B encoder On/Off When you turn this option On, the PCSincl

Signal Name Direction Descriptiontx_digitalreset[<n>-1:0] Input When asserted, reset all blocks in the TX PCS. Ifyour design includes bonded TX

When you enable the simplified data interface and enable the rate match FIFO status ports, the rate matchFIFO bits map to the high-order bits of the d

Status Condition Protocol Mapping of Status Flags to RX Data ValueEmptyPHY IP Core for PCIExpress (PIPE)Basic double widthRXD[62:62] = rx_rmfifostatus

Status Condition Protocol Mapping of Status Flags to RX Data ValueDeletionBasic double widthSerial RapidIO double widthRXD[62:62] = rx_rmfifostatus[1:

Parameter Range DescriptionRX word aligner modebit_slipsync_smmanualSpecifies one of the following 3 modes for theword aligner:• Bit_slip : You can us

Parameter Range DescriptionEnable rx_std_wa_patternalign port On/Off Enables the optional rx_std_wa_patterna-lign control input port. A rising edge on

Parameter Range DescriptionEnable rx_std_bitrev_ena port On/Off When you turn this option On, asserting rx_std_bitrev_ena control port causes the RXda

PRBS VerifierYou can use the PRBS pattern generators for verification or diagnostics. The pattern generator blockssupport the following patterns:• Pse

PCS-PMA Width8-Bit 10-Bit 16-Bit 20-BitPRBS-10XPRBS 15X X X XPRBS 23X X XPRBS 31X X X XUnlike the 10G PRBS verifier, the Standard PRBS verifier uses t

PCS-PMA Width PRBS Patterns PRBS Pattern Select Word Aligner Size Word Aligner Pattern20-bitPRBS 7 3’b000 3’b100 0x0000043040PRBS 23 3’b001 3’b110 0x0

Offset OffsetBits R/W Name Description0xA3 [15:0] R/W Word Aligner Pattern[15:0]Stores the least significant 16 bitsfrom the word aligner pattern assp

Figure 3-7: Arria V GT Clock Generation and Distribution10GBASE-R Transceiver Channel - Arria V GT TX PCS(soft)RX PCS(soft)TX PMA(hard)RX PMA(hard)TX

10G PCS Parameters for Arria V GZ Native PHYThis section shows the complete datapath and clocking for the 10G PCS and defines parameters availablein t

Table 14-23: General and Datapath ParametersParameter Range Description10G PCS protocol modebasicinterlakensfi5teng_baserteng_sdiSpecifies the protoco

Table 14-24: 10G TX FIFO ParametersParameter Range DescriptionTX FIFO ModeInterlakenphase_compregisterSpecifies one of the following 3 modes:• interla

Parameter Range DescriptionEnable tx_10g_fifo_pfull port On/Off When you turn this option On , the 10GPCS includes the active high tx_10g_fifo_pfull p

Table 14-25: 10G RX FIFO ParametersParameter Range DescriptionRX FIFO ModeInterlakenclk_compphase_compregisterSpecifies one of the following 3 modes:•

Parameter Range DescriptionEnable RX FIFO alignment word deletion(interlaken)On/Off When you turn this option On, allalignment words (sync words),incl

Parameter Range DescriptionEnable rx_10g_fifo_insert port(10GBASE-R)On/Off When you turn this option On, the 10GPCS includes the rx_10g_fifo_insertpor

Table 14-26: Interlaken Frame Generator ParametersParameter Range Descriptionteng_tx_framgen_enable On/Off When you turn this option On, theframe gene

zation process again. Lock status is available to the FPGA fabric. The following table describes theInterlaken frame synchronizer parameters.Table 14-

Parameter Range DescriptionEnable rx_10g_frame_skip_err port On/Off When you turn this option On, the 10GPCS includes the rx_10g_frame_skip_err output

Figure 3-8: Arria V GZ Clock Generation and Distributionpll_ref_clk 644.53125 MHz10.3125 Gbps serial257.8125 MHz257.8125 MHz156.25 MHz10GBASE-R Hard

10GBASE-R BER CheckerThe BER monitor block conforms to the 10GBASE-R protocol specification as described in IEEE802.3-2008 Clause-49. After block lock

Parameter Range DescriptionEnable TX 64b/66b encoder On/Off When you turn this option On, the 10G PCSincludes the TX 64b/66b encoder.Enable TX 64b/66b

Table 14-32: Interlaken Disparity Generator and Checker ParametersParameter Range DescriptionEnable Interlaken TX disparity generator On/Off When you

GearboxThe gearbox adapts the PMA data width to a wider PCS data width when the PCS is not two or four timesthe PMA width.Table 14-34: Gearbox Paramet

Table 14-35: PRBS ParametersParameter Range DescriptionEnable rx_10g_prbs ports On/Off When you turn this option On, the PCSincludes the rx_10g_prbs_d

Offset Bits R/W Name Description0x135[15:12] R/WSquare Wave PatternSpecifies the number of consecutive 1sand 0s. The following values areavailable: 1,

Offset Bits R/W Name Description0x15E[14] R/WRX PRBS 7 EnableEnables the PRBS-7 polynomial in thereceiver.[13] R/WRX PRBS 23 EnableEnables the PRBS-23

In addition you have the following options:• You can toggle the Data Pattern Select bit switch between two data patterns.• You can change the value of

Figure 14-5: Arria V GZ Native PHY Common Interfacestx_pll_refclk[<r>-1:0]tx_pma_clkout[<n>-1:0]rx_pma_clkout[<n>-1:0]rx_cdr_refclk[

Name Direction DescriptionResetspll_powerdown[<n> -1:0]Input When asserted, resets the TX PLL. Active high,edge sensitive reset signal. By defau

Figure 3-9: Stratix IV Clock Generation and Distributionpll_ref_clk 644.53125 MHz10.3125 Gbps serial516.625 MHz257.8125 MHz516.625 MHz257.8125 MHz156.

Name Direction Descriptiontx_parallel_data[<n> 64-1:0]Input PCS TX parallel data. Used when you enableeither the Standard or 10G datapath. For t

Name Direction Descriptiontx_pma_txdetectrx Input When asserted, the RX detect block in the TXPMA detects the presence of a receiver at theother end o

Name Direction Descriptionrx_is_lockedtoref[<n> -1:0]Output When asserted, the CDR is locked to theincoming reference clock.rx_clkslip[<n>

TX Data Word Descriptiontx_parallel_data[10] Specifies the current disparity as follows:• 1'b0 = positive• 1'b1 = negativeSignal Definitions

RX Data Word Descriptionrx_parallel_data[10] Synchronization statusrx_parallel_data[11] Disparity errorrx_parallel_data[12] Pattern detectrx_parallel_

Figure 14-6: Standard PCS InterfacesClocksWordAlignerPhaseCompensationFIFOByteOrderingRateMatch FIFOPolarityInversionPMAPortsStandard PCS Interface Po

Name Dir Synchro‐nous to tx_std_coreclkin/rx_std_coreclkinDescriptionrx_std_pcfifo_empty[<n>-1:0]Output Yes RX phase compensation FIFO statusemp

Name Dir Synchro‐nous to tx_std_coreclkin/rx_std_coreclkinDescriptionrx_std_polinv[<n>-1:0]Input No Polarity inversion for the 8B/10B decoder,Wh

Name Dir Synchro‐nous to tx_std_coreclkin/rx_std_coreclkinDescriptiontx_std_bitslipboun-darysel[5<n>-1:0]Input No BitSlip boundary selection sig

Name Dir Synchro‐nous to tx_std_coreclkin/rx_std_coreclkinDescriptiontx_std_elecidle[<n>-1:0]Input When asserted, enables a circuit to detect ad

Figure 3-10: Stratix V Clock Generation and Distributionpll_ref_clk 644.53125 MHz10.3125 Gbps serial257.8125 MHz257.8125 MHz156.25 MHz10GBASE-R Hard

Figure 14-7: Arria V Native PHY 10G PCS InterfacesClocksFrameGeneratorTX FIFORX FIFOBlockSynchronizerFrameSynchronizerBit-SlipGearboxFeature64B/66BBER

Name Dir Synchro‐nous to tx_10g_coreclkin/rx_10g_coreclkinDescriptiontx_10g_coreclkin[<n>-1:0]Input —TX parallel clock input that drive the writ

Name Dir Synchro‐nous to tx_10g_coreclkin/rx_10g_coreclkinDescriptiontx_10g_control[9<n>-1:0] (continued)• [2]: Inversion signal, must always be

Name Dir Synchro‐nous to tx_10g_coreclkin/rx_10g_coreclkinDescriptiontx_10g_data_valid[<n>-1:0]Input YesWhen asserted, indicates if tx_data is v

Name Dir Synchro‐nous to tx_10g_coreclkin/rx_10g_coreclkinDescriptionrx_10g_control[10<n>-1:0]Output YesRX control signals for the Interlaken, 1

Name Dir Synchro‐nous to tx_10g_coreclkin/rx_10g_coreclkinDescriptionrx_10g_control[10<n>-1:0] (continued)Basic mode: 67-bit mode with Block Syn

Name Dir Synchro‐nous to tx_10g_coreclkin/rx_10g_coreclkinDescriptionrx_10g_data_valid[<n>-1:0]Output Yes Active valid data signal with the foll

Name Dir Synchro‐nous to tx_10g_coreclkin/rx_10g_coreclkinDescriptionRx_10g_fifo_insert[<n>-1:0] Output Yes Active-high 10G BaseR R

Name Dir Synchro‐nous to tx_10g_coreclkin/rx_10g_coreclkinDescriptionrx_10g_frame_lock[<n>-1:0]Output No For the Interlaken protocol, asserted t

Name Dir Synchro‐nous to tx_10g_coreclkin/rx_10g_coreclkinDescriptionrx_10g_frame_skip_err[<n>-1:0]Output No For the Interlaken protocol, assert

Table 3-15: Avalon-MM PHY Management InterfaceSignal Name Direction Descriptionphy_mgmt_clk Input The clock signal that controls the Avalon-MMPHY mana

Name Dir Synchro‐nous to tx_10g_coreclkin/rx_10g_coreclkinDescriptionBit-Slip Gearbox Feature Synchronizerrx_10g_bitslip[<n>-1:0]Input No User c

SDC Timing Constraints of Arria V GZ Native PHYThis section describes SDC examples and approaches to identify false timing paths.The Quartus II softwa

Example 14-2: Using the max_delay Constraint to Identify Asynchronous InputsYou can use the set_max_delay constraint on a given path to create a const

Example 14-5: Overriding Logical Channel 0 Channel Assignment Restrictions in Arria V GZDevice for ×6 or ×N BondingIf you are using ×6 or ×N bonding,

Cyclone V Transceiver Native PHY IP CoreOverview152015.01.19UG-01080SubscribeSend FeedbackThe Cyclone V Transceiver Native PHY IP Core provides direct

In a typical design, the separately instantiated Transceiver PHY Reset Controller drives reset signals toNative PHY and receives calibration and locke

Note: The Cyclone V Transceiver Native PHY provides presets for CPRI, GIGE, and the Low LatencyStandard PCS. The presets specify the parameters requir

Name Range DescriptionBonding mode Non-bonded orx1Bonded or xNIn Non-bonded or x1 mode, each channel isassigned a PLL.If one PLL drives multiple chann

Table 15-3: PMA Options Parameter Range DescriptionData rate DeviceDependentSpecifies the data rate. The maximum data rate is12.5 Gbps.TX local clock

Parameter Range DescriptionUse external TX PLL On/Off When you turn this option On, the Native PHYdoes not include TX PLLs. Instead, the NativePHY inc

Word Addr Bit R/W Name Description0x021 [31:0] RW cal_blk_powerdown Writing a 1 to channel <n> powersdown the calibration block forchannel <n

Parameter Range DescriptionPLL base data rate DeviceDependentShows the base data rate of the clock input to theTX PLL.The PLL base data rate is comput

Table 15-6: RX PMA Parameters Parameter Range DescriptionEnable CDR dynamic reconfigura‐tionOn/Off When you turn this option On, you candynamically c

Standard PCS ParametersThis section illustrates the complete datapath and clocking for the Standard PCS and defines theparameters available to enable

Table 15-7: General and Datapath Parameters Parameter Range DescriptionStandard PCS protocol modebasiccprigigeSpecifies the protocol that you intend

Parameter Range DescriptionEnable Standard PCS low latencymodeOn/Off When you turn this option On, all PCS functionsare disabled except for the phase

Parameter Range DescriptionEnable rx_std_pcfifo_full port On/Off When you turn this option On, the RX Phasecompensation FIFO outputs a FIFO full statu

Parameter Range DescriptionByte ordering patternwidth8–10Shows width of the pattern that you must specify. Thiswidth depends upon the PCS width and wh

Related InformationTransceiver Architecture in Cyclone V DevicesByte Serializer and DeserializerThe byte serializer and deserializer allow the PCS to

Parameter Range DescriptionEnable TX 8B/10B disparitycontrolOn/Off When you turn this option On, the PCS includesdisparity control for the 8B/10B enco

Note: If you have the auto-negotiation state machine in your transceiver design, please note that the ratematch FIFO is capable of inserting or deleti

Interlaken PHY IP Core...7-1Interlaken PHY Device Family Support...

Word Addr Bit R/W Name Description0x044[31:0] RW reset_fine_control You can use the reset_fine_control register to create your ownreset sequence. The

Status Condition Protocol Mapping of Status Flags to RX Data ValueEmptyPHY IP Core for PCIExpress (PIPE)Basic double widthRXD[62:62] = rx_rmfifostatus

Status Condition Protocol Mapping of Status Flags to RX Data ValueDeletionBasic double widthSerial RapidIO double widthRXD[62:62] = rx_rmfifostatus[1:

Parameter Range DescriptionRX word aligner mode bit_slipsync_smmanualSpecifies one of the following 3 modes for theword aligner:• Bit_slip: You can us

Parameter Range DescriptionEnable rx_std_wa_patternalignportOn/Off Enables the optional rx_std_wa_patternaligncontrol input port.Enable rx_std_wa_a1a2

Parameter Range DescriptionEnable TX polarity inversion On/Off When you turn this option On, the tx_std_polinv port controls polarityinversion of TX p

Parameter Range DescriptionEnable rx_std_signaldetect port On/Off When you turn this option On, theoptional rx_std_signaldetect outputport is enabled.

Figure 15-3: Common Interface Portstx_pll_refclk[<r>-1:0]tx_pma_clkout[<n>-1:0]rx_pma_clkout[<n>-1:0]rx_cdr_refclk[<r>-1:0]Clo

Name Direction Descriptionpll_powerdown[<p>-1:0]Input When asserted, resets the TX PLL. Activehigh, edge sensitive reset signal. Bydefault, the

Name Direction DescriptionTX and RX serial portstx_serial_data[<n>-1:0]Output TX differential serial output data.rx_serial_data[<n>-1:0]In

Name Direction Descriptionrx_clkslip[<n>-1:0]InputWhen you turn this signal on, thedeserializer performs a clock slipoperation to achieve word a

Word Addr Bit R/W Name Description0x067 [31:0] RO pma_rx_is_lockedtoref When asserted, indicates that the RXCDR PLL is locked to the referenceclock. B

TX Data Word Descriptiontx_parallel_data[10] Specifies the current disparity as follows:• 1'b0 = positive• 1'b1 = negativeSignal Definitions

RX Data Word Descriptionrx_parallel_data[12] Pattern detectrx_parallel_data[14:13] The following encodings are defined:• 2’b00: Normal data• 2’b01: De

Figure 15-4: Standard PCS Interfacestx_std_clkout[<n>-1:0] rx_std_clkout[<n>-1:0]tx_std_coreclkin[<n>-1:0]rx_std_coreclkin[<n>

Name Dir Synchronous totx_std_coreclkin/rx_std_coreclkinDescriptiontx_std_pcfifo_full[<n>-1:0]Output Yes TX phase compensation FIFO status fullf

Name Dir Synchronous totx_std_coreclkin/rx_std_coreclkinDescriptiontx_std_polinv[<n>-1:0]Input No Polarity inversion, part of 8B10B encoder,When

Name Dir Synchronous totx_std_coreclkin/rx_std_coreclkinDescriptionrx_st_wa_patternalignInput No Active when you place the word aligner inmanual mode.

The Quartus II software reports timing violations for asynchronous inputs to the Standard PCS. Becausemany violations are for asynchronous paths, they

For non-bonded clocks, each channel and each TX PLL has a separate dynamic reconfiguration interfaces.The MegaWizard Plug-In Manager provides informat

Transceiver Reconfiguration Controller IP CoreOverview162015.01.19UG-01080SubscribeSend FeedbackThe Altera Transceiver Reconfiguration Controller dyna

Area Feature Stratix V Arria V Arria V GZ Cyclone VTransceiverChannel/PLLReconfigurationRX CDR reconfiguration Yes Yes Yes YesReconfiguration of PCS b

Word Addr Bit R/W Name Description0x083[5:0] R BER_COUNT[5:0] For Stratix IV devices only, recordsthe bit error rate (BER). From block:BER monitor[13:

Figure 16-1: Transceiver Reconfiguration Controllerto and fromEmbeddedControllerTX and RXSerial DataAvalon-MM master interfaceTransceiver Reconfigurat

The Transceiver Reconfiguration Controller provides two modes to dynamically reconfigure transceiversettings:• Register Based—In this access mode you

Transceiver Reconfiguration Controller Performance and ResourceUtilizationThis section describes the approximate device resource utilization for a the

Parameterizing the Transceiver Reconfiguration Controller IP Core inQsysComplete the following steps to configure the Transceiver Reconfiguration Cont

Name Value DescriptionTransceiver Calibration FunctionsEnable offset cancellation OnWhen enabled, the Transceiver Reconfigura‐tion Controller includes

Name Value DescriptionEnable PLL reconfigurationsupport blockOn/Off When enabled, the Transceiver Reconfigura‐tion Controller includes logic to perfor

Signal Name Direction Descriptionreconfig_mif_read Output When asserted, signals an Avalon-MM readrequest.reconfig_mif_readdata[15:0] Input The read d

Signal Name Direction Descriptiontx_cal_busy OutputThis optional signal is asserted while initial TX calibra‐tion is in progress and no further reconf

Table 16-7: Reconfiguration Management InterfaceSignal Name Direction Descriptionmgmt_clk_clk Input Avalon-MM clock input. The frequency range for the

Signal Name Direction Descriptionreconfig_mgmt_read Input Read signal. Active high.Related InformationAvalon Interface SpecificationsTransceiver Recon

Signal Name Direction Descriptionreconfig_from_xcvr [(<n>/4)17-1:0]Output Reconfiguration RAM. The PHY device drives thisRAM data to the transce

The following table lists the address range for the Transceiver Reconfiguration Controller and the reconfi‐guration and signal integrity modules. The

Auxiliary Transmit (ATX) PLL CalibrationATX calibration tunes the parameters of the ATX PLL for optimal performance. This function runs onceafter powe

Reconfig Addr Bits R/W Register Name Description7’h0A[9] Rcontrol and statusError. When asserted, indicates an error.This bit is asserted if any of th

Offset Bits R/W Register Name Description0x3 [4:0] RW Pre-emphasis second post-tapThe following encodings are defined:• 5’b00000 and 5’b10000: 0• 5’b0

EyeQ uses a phase interpolator and sampler to estimate the vertical and horizontal eye opening using thevalues that you specify for the horizontal pha

Note: All undefined register bits are reserved.Table 16-12: EyeQ Offsets and ValuesNote: The default value for all the register bits mentioned in this

Offset Bits R/W Register Name Description0x3[15:4] RMW Reserved You should not modify these bits. To update thisregister, first read the value of this

as a diagnostic tool to perform in-system link analysis without interrupting the link traffic. The stepsbelow provide BERB operation example:• Write 3

Reconfig Addr Bits R/W Register Name Description7’h1A[9] Rcontrol and statusError.When asserted, indicates an invalidchannel or address.[8] R Busy. Wh

Offset Bits R/W Register Name Description0x4[3] RW tap 4 polaritySpecifies the polarity of the fourth post tap asfollows:• 0: negative polarity• 1: po

1588 Delay RequirementsThe 1588 protocol requires symmetric delays or known asymmetric delays for all external connections.In calculating the delays f

The register-based write to turn on continuous adaptive DFE for logical channel 0 is as shown in thefollowing example:Example 16-1: Register-Based Wri

1. Read the DFE control and status register busy bit (bit 8) until it is clear.2. Write the logical channel number of the channel to be updated to the

Table 16-15: AEQ RegistersReconfig Addr Bits R/W Register Name Description7’h28 [9:0] RW logical channel number The logical channel number of the AEQh

Table 16-16: AEQ Offsets and ValuesOffset Bits R/W Register Name Description Default Value0x0[8] R adapt_done When asserted, indicates that adaptation

Table 16-17: ATX Tuning RegistersATX Addr Bits R/W Register Name Description7’h30 [9:0] RW logical channel number The logical channel number. TheTrans

Transceiver Reconfiguration Controller PLL ReconfigurationYou can use the PLL reconfiguration registers to change the reference clock input to the TX

Figure 16-5: Reconfiguration Tab of Native Transceiver PHYsNote: If you dynamically reconfigure PLLs, you must provide your own reset logic by includi

Related Information• Transceiver Reset Control in Stratix V Devices• Transceiver Reset Control and Power-Down in Arria V Devices• Transceiver Reset Co

Reconfig Addr Bits R/W Register Name Description7’h44 [15:0] RW data Specifies the read or write data.Note: All undefined register bits are reserved.T

DCD runs automatically at power up. After power up, you can rerun DCD by writing to the DCD controlregister. Altera recommends that you run DCD calibr

set_clock_uncertainty -from [get_clocks {*siv_alt_pma|pma_ch*.pma_direct|receive_pcs*|clkout}] -to pll_ref_clk -setup 0.1set_clock_uncertainty -from [

Channel ReconfigurationIf you turn on Enable channel/PLL reconfiguration in the Transceiver Reconfiguration Controller GUI,you can change the followin

Transceiver Reconfiguration Controller Streamer Module RegistersThe Streamer module defines the following two modes for channel and PLL reconfiguratio

PHY Addr Bits R/W Register Name Description[1] W Read. Writing a 1 to this bit triggers a readoperation. This bit is self clearing.[0] W Write. Writin

Offset Bits R/W Register Name Description0x2[4] RO MIF or Channel mismatchWhen asserted, indicates the MIF typespecified is incorrect. For example, th

MIF GenerationThe MIF stores the configuration data for the transceiver PHY IP cores. The Quartus II softwareautomatically generates MIFs after each s

The Quartus II software automatically generates MIF for all designs that support POF generation with thefollowing exceptions:• Designs that use bonded

Table 16-27: Required Lines for All MIFsLine Number Description Content Includes0 Specifies start of the reconfigurationMIFStart of MIF opcode1 Specif

information necessary to change from 1 Gbps to 5 Gbps and from 5 Gbps to 1 Gbps. You can use thesefiles to reduce reconfiguration and simulation times

Example 16-6: Two Partial MIF filesThe following example shows and the reduced MIF file, to_MIF_A created by the xcvr_diffmifgen utility:Example 16-7:

Reduced MIF CreationThe procedure described here is an alternative way to generate a reduced MIF file. You can also use thexcvr_diffmifgen Utility. Fo

Note: The SDC timing constraints and approaches to identify false paths listed for Stratix V Native PHYIP apply to all other transceiver PHYs listed i

Example 16-8: Register-Based Write of Logical Channel 0 VOD SettingSystem Console is used for the following settings:#Setting logical channel 0write_3

Direct Write ReconfigurationFollow these steps to reconfigure a transceiver setting using a series of Avalon-MM direct writes.1. Write the logical cha

write_32 0x3A 0x5#Read the busy bit to determine when the operation completesread_32 0x3a#Incrementing Streamer offset register offset addresswrite_32

write_32 0x3B 0x0#Setting data register with the MIF base addresswrite_32 0x3C 0x100#Writing all data to the Streamerwrite_32 0x3A 0x1#Setting Streame

a. Sync badcg, (offset 0xA1, bits[15:14])b. Enable Comma Detect, (offset 0xA1, bit[13])c. Enable Polarity, (offset, 0xA1, bit[11])8. Now, you must set

a. PRBS TX Enable, (0x97, bit[9])b. PRBS Pattern Select, (0x97, bit[8:6])7. Assert the channel reset to begin testing on the new PRBS pattern.Enabling

write_32 0x3A 0x6 //write the control and status register //with a value of 0x6 to address 0x3A to initiate a readread_32 0x3C //Read

//Generator selection and setupread_32 0x3A //Read the control and status register //busy bit[8] until it is clearwrite_32 0x38 0x0 //wri

The transceiver PHY IP cores create a separate reconfiguration interface for each channel and each TXPLL. Each transceiver PHY IP core reports the num

Figure 16-10: Transceiver Reconfiguration Controller Interface BundlesThe following figure shows a design with two transceiver PHY IP core instances,

Backplane Ethernet 10GBASE-KR PHY IP Corewith Early Access FEC Option42015.01.19UG-01080SubscribeSend FeedbackThe Backplane Ethernet 10GBASE-KR PHY Me

Two PHY IP Core Instances Each with Four Bonded ChannelsThis section describes logical channel numbering for two transceiver PHY instances, each with

Logical Interface Number PHY Instance, Interface, or PLL12-15 Instance 1, TX PLL. The Fitter assigns all 4 logical TX PLLs to asingle physical PLL.One

Note: Because all of the channels in a transceiver bank share a PLL, this original numbering allows theFitter to select the optimal CMU PLL from a pla

Table 16-32: Initial Number of Eight Bonded ChannelsInstance Channel Logical Channel NumberInstance 0Channel 0 0Channel 1 1Channel 2 2Channel 3 3CMU 0

Figure 16-12: Correct ConnectionsTransceiver ReconfigurationControllerTransceiver Bank3 TransceiverChannels3 TransceiverChannels10 GBASE-R(unused)(unu

The Quartus II Fitter can merge the TX PLLs for multiple transceiver PHY IP cores under the followingconditions:• The PLLs connect to the same reset p

post-CDR mode, received data passes through the RX CDR and then loops back to the TX output buffer.The RX data is also available to the FPGA fabric. I

Figure 16-16: Serial LoopbackTx P C SRx P C SFPGAFabricTx PMAtx_dataoutSerializerRx PMASerialloopbackDe-serializerTo FPGA fabricfor verificationTran

Transceiver PHY Reset Controller IP Core172015.01.19UG-01080SubscribeSend FeedbackThe Transceiver PHY Reset Controller IP Core is a highly configurabl

Figure 17-1: Typical System Diagram for the Transceiver PHY Reset Controller IP CoreThis figure illustrates the typical use of Transceiver PHY Reset C

Figure 4-1: 10GBASE-KR PHY MegaCore Function and Supporting BlocksAltera Device with 10.3125+ Gbps Serial Transceivers10GBASE-KR PHY MegaCore Function

Related Information• Transceiver Reset Control in Arria V Devices• Transceiver Reset Control in Cyclone V Devices• Transceiver Reset Control in Strati

Parameterizing the Transceiver PHY Reset Controller IPThis section lists steps to configure the Transceiver PHY Reset Controller IP Core in the IP Cat

Name Range DescriptionEnable TX PLL reset control On /Off When On, the Transceiver PHY ResetController IP core enables the reset control ofthe TX PLL.

Name Range DescriptionRX ChannelEnable RX channel reset control On /Off When On, the Transceiver PHY ResetController enables the control logic andasso

Figure 17-2: Transceiver PHY Reset Controller IP Core Top-Level SignalsGenerating the IP core creates signals and ports based on your parameter settin

Signal Name Direction Clock Domain Descriptionrx_cal_busy[<n> -1:0]Input Asynchronous This is calibration status signal from theTransceiver PHY

Signal Name Direction Clock Domain Descriptiontx_digital-reset[<n>-1:0]Output Synchronous to theTransceiver PHYReset Controllerinput clock.Digit

Signal Name Direction Clock Domain Descriptionrx_digital-reset[<n> -1:0]Output Synchronous to theTransceiver PHYReset Controllerinput clock.Digi

Figure 17-3: Physical Routing Delay Skew in Bonded ChannelsPHY ResetControllerTXChannel[ n - 1]TXChannel[1]TXChannel[0]Bonded TXChannelstx_digitalrese

For more information about the set_max_skew constraint, refer to the SDC and TimeQuest API ReferenceManual.Related InformationSDC and TimeQuest API Re

10GBASE-KR PHY Release InformationTable 4-1: 10GBASE-KR PHY Release InformationItem DescriptionVersion 13.1Release Date November 2013Ordering CodesIP-

Transceiver PLL IP Core for Stratix V, Arria V,and Arria V GZ Devices182015.01.19UG-01080SubscribeSend FeedbackWhen a fractional PLL functions as the

Figure 18-1: IP Cores Required for Designs Using the Fractional PLLThe following figure show the IP Cores you can instantiate to create designs that u

Parameterizing the Transceiver PLL PHYThe IP Catalog provides the following Transceiver PLL IP Cores: Arria V Transceiver, Arria V GZTransceiver PLL,

Name Value DescriptionReference clock frequency Variable Specifies the frequency of the PLL inputreference clock. The PLL must generate anoutput frequ

Related InformationComponent Interface Tcl ReferenceUG-010802015.01.19Transceiver PLL Signals18-5Transceiver PLL IP Core for Stratix V, Arria V, and A

Analog Parameters Set Using QSF Assignments192015.01.19UG-01080SubscribeSend FeedbackYou specify the analog parameters using the Quartus II Assignment

a. Double-click in the Assignment Name column and scroll to the bottom of the availableassignments.b. Select VCCR_GXB/VCCT_GXB Voltage.c. In the Value

Assign ToPin - TX & RX serial dataXCVR_REFCLK_PIN_TERMINATIONPin Planner and Assignment Editor NameTransceiver Dedicated Refclk Pin TerminationDes

XCVR_VCCR_ VCCT_VOLTAGEPin Planner and Assignment Editor NameVCCR_GXBVCCT_GXB VoltageDescriptionConfigures the VCCR_GXB and VCCT_GXB voltage for an GX

PLL_BANDWIDTH_PRESETPin Planner and Assignment Editor NamePLL Bandwidth PresetDescriptionSpecifies the PLL bandwidth preset settingOptions• Auto• Low•

Parameterizing the Custom PHY... 9-3General

The following table shows the typical expected resource utilization for selected configurations using thecurrent version of the Quartus II software ta

XCVR_ANALOG_SETTINGS_PROTOCOL assigns a value to XCVR_RX_BYPASS_EQ_STAGES_234. If you alsoassign a value to this parameter, a Quartus II Fitter error

XCVR_RX_LINEAR_EQUALIZER_CONTROLPin Planner and Assignment Editor NameReceiver Linear Equalizer ControlDescriptionStatic control for the continuous ti

1Assign ToPin - RX serial dataXCVR_RX_SD_ONPin Planner and Assignment Editor NameReceiver Cycle Count Before Signal Detect Block Declares Presence Of

Assign ToPin - RX serial dataXCVR_TX_COMMON_MODE_VOLTAGEPin Planner and Assignment Editor NameTransmitter Common Mode Driver VoltageDescriptionTransmi

Options• TRUE• FALSEAssign ToPin - TX serial dataXCVR_TX_RX_DET_MODEPin Planner and Assignment Editor NameTransmitter Receiver Detect Block ModeDescri

DescriptionWhen set to DYNAMIC_CTL, the PCS block controls the VOD and pre-emphasis coefficients for PCIExpress. When this assignment is set to RAM_

Options• 85_Ohms• 100_Ohms• 120_Ohms• 150_Ohms• External_ResistorAssign ToPin - TX & RX serial dataXCVR_REFCLK_PIN_TERMINATIONPin Planner and Assi

a value to this setting and XCVR_ANALOG_SETTINGS_PROTOCOL results in a Quartus II Fitter error as shownin the following example:Error (21215)Error res

DescriptionConfigure the VCCA_GXB voltage for a GXB I/O pin by specifying the intended VCCA_GXB voltage fora GXB I/O pin. If you do not make this assi

DescriptionSpecifies the CDR bandwidth preset settingOptions• Auto• Low• Medium• HighAssign ToPLL instancemaster_ch_numberPin Planner and Assignment E

Related Information• 10GBASE-KR Link Training Parameters on page 4-5• 10GBASE-KR Auto-Negotiation and Link Training Parameters on page 4-7• 10GBASE-R

Options• Auto• Low• Medium• HighAssign ToPLL instancereserved_channelPin Planner and Assignment Editor NameParameter (Assignment Editor Only)Descripti

XCVR_ANALOG_SETTINGS_PROTOCOL assigns a value to XCVR_RX_BYPASS_EQ_STAGES_234. If you alsoassign a value to this parameter, a Quartus II Fitter error

Assign ToPin - RX serial dataXCVR_RX_LINEAR_EQUALIZER_CONTROLPin Planner and Assignment Editor NameReceiver Linear Equalizer ControlDescriptionStatic

Assign ToPin - RX serial dataXCVR_RX_SD_ENABLEPin Planner and Assignment Editor NameReceiver Signal Detection Unit Enable/DisableDescriptionEnables or

Options0–16Assign ToPin - RX serial dataXCVR_RX_SD_THRESHOLDPin Planner and Assignment Editor NameReceiver Signal Detection Voltage ThresholdDescripti

XCVR_TX_PRE_EMP_PRE_TAP_USERPin Planner and Assignment Editor NameTransmitter Pre-emphasis Pre-Tap userDescriptionSpecifies the TX pre-emphasis pretap

Note: This parameter must be set in conjunction with XCVR_TX_VOD, XCVR_TX_PRE_EMP_2ND_POST_TAP,and XCVR_TX_PRE_EMP_PRE_TAP. All combinations of these

Assign ToPin - TX serial dataRelated InformationSolution rd02262013_691This solution provides the mapping of the Transceiver Toolkit pretap settings t

Related InformationArria V GZ Device DatasheetXCVR_TX_RX_DET_ENABLEPin Planner and Assignment Editor NameTransmitter Receiver Detect Block EnableDescr

Assign ToPin - TX serial dataXCVR_TX_VODPin Planner and Assignment Editor NameTransmitter Differential Output VoltageDescriptionDifferential output vo

Name Value DescriptionVMINRULE0-63 Specifies the minimum VOD. The default value is 9which represents 165 mV.VODMINRULE0-63 Specifies the minimum VOD f

Analog Settings for Cyclone V DevicesXCVR_IO_PIN_TERMINATIONPin Planner and Assignment Editor NameTransceiver I/O Pin TerminationDescriptionSpecifies

Assign ToPin - PLL refclk pinXCVR_TX_SLEW_RATE_CTRLPin Planner and Assignment Editor NameTransmitter Slew Rate ControlDescriptionSpecifies the slew ra

CDR_BANDWIDTH_PRESETPin Planner and Assignment Editor NameCDR Bandwidth PresetDescriptionSpecifies the CDR bandwidth preset settingOptions• Auto• Low•

you cannot assign a value for any settings that this parameter controls. For example, for PCIe, theXCVR_ANALOG_SETTINGS_PROTOCOL assigns a value to XC

DescriptionStatic control for the continuous time equalizer in the receiver buffer. The equalizer has 3 settings from 0–2 corresponding to the increas

DescriptionNumber of parallel cycles to wait before the signal detect block declares loss of signal. Only used for thePCIe PIPE PHY, SATA, and SAS pro

The signal detect output is high when the receiver peak-to-peak differential voltage (diff p-p) > Vth x 4.For example, a setting of 6 translates to

XCVR_TX_RX_DET_ENABLEPin Planner and Assignment Editor NameTransmitter Receiver Detect Block EnableDescriptionEnables or disables the receiver detecto

XCVR_TX_VOD_PRE_EMP_CTRL_SRCPin Planner and Assignment Editor NameTransmitter VOD Pre-emphasis Control SourceDescriptionWhen set to DYNAMIC_CTL, the

Options• 0-15• 12 (TX)• 9 (RX)Assign ToPin - TX & RX serial dataXCVR_IO_PIN_TERMINATIONPin Planner and Assignment Editor NameTransceiver I/O Pin T

10GBASE-KR Auto-Negotiation and Link Training ParametersTable 4-5: Auto Negotiation and Link Training SettingsName Range DescriptionAN_PAUSE Pause Abi

Options• AC_COUPLING• DC_COUPLING_INTERNAL_100_OHMS• DC_COUPLING_EXTERNAL_RESISTORAssign ToPin - PLL refclk pinXCVR_RX_BYPASS_EQ_STAGES_234Pin Planner

DescriptionSpecifies the slew rate of the output signal. The valid values span from the slowest rate to fastest rate with1 representing the slowest ra

Assign ToPin - TX & RX serial dataRelated InformationStratix V Device DatasheetAnalog Settings Having Global or Computed Default Values for Strati

Example 19-4: Overriding Default Master ChannelExample: set_parameter -name master_ch_number 4 -to"<design>:inst|altera_xcvr_native_sv:test

DescriptionAllows you to override the default channel placement of x8 variants. For the PHY IP Core for PCI Express(PIPE), you can use this QSF assign

• BASIC• CEI• CPRI• INTERLAKEN• PCIE_GEN1• PCIE_GEN2• PCIE_GEN3• QPI• SFIS• SONET• SRIO• TENG_1588• TENG_BASER• TENG_SDI• XAUIAssign ToPin - TX and RX

Assign ToPin - RX serial dataXCVR_RX_LINEAR_EQUALIZER_CONTROLPin Planner and Assignment Editor NameReceiver Linear Equalizer ControlDescriptionStatic

XCVR_GT_TX_COMMON_ MODE_VOLTAGEPin Planner and Assignment Editor NameGT Transmitter Common Mode Driver VoltageDescriptionTransmitter common-mode drive

Options• ON• OFFAssign ToPin - TX serial dataRelated InformationStratix V Device DatasheetXCVR_GT_TX_PRE_EMP_ PRE_TAPPin Planner and Assignment Editor

DescriptionReceiver buffer common-mode voltage.Note: Contact Altera for using this assignment.Related InformationHow to Contact Altera on page 21-42XC

Parameter Name Options DescriptionReference clock frequency 644.53125MHz322.265625MHzSpecifies the input reference clock frequency.The default is 322.

XCVR_RX_SD_OFFPin Planner and Assignment Editor NameReceiver Cycle Count Before Signal Detect Block Declares Loss Of SignalDescriptionNumber of parall

• SDLV_25MV=2• SDLV_20MV=1• SDLV_15MV=0For the PCIe PIPE PHY, SATA, and SAS.The signal detect output is high when the receiver peak-to-peak differenti

Related Information• Solution rd02262013_691This solution provides the mapping of the Transceiver Toolkit pretap settings to the Quartus IItransceiver

DescriptionSpecifies the second post-tap setting value.Note: This parameter must be set in conjunction with XCVR_TX_VOD, XCVR_TX_PRE_EMP_1ST_POST_TAP,

DescriptionInverts the transmitter pre-emphasis pretap. Specifies the TX pre-emphasis pretap setting value, includinginversion.Options• TRUE• FALSEAss

Options• TRUE• FALSEAssign ToPin - TX serial dataXCVR_TX_RX_DET_MODEPin Planner and Assignment Editor NameTransmitter Receiver Detect Block ModeDescri

DescriptionDifferential output voltage setting. The values are monotonically increasing with the driver main tapcurrent strength.Note: This parameter

Migrating from Stratix IV to Stratix V DevicesOverview202013.12.20UG-01080SubscribeSend FeedbackPreviously, Altera provided the ALTGX megafunction as

Loopback Mode Stratix IV Stratix VReverse serial loopback (pre-and post-CDR)On the Loopback tab of theALTGX MegaWizard Plug-InManager, select either p

Stratix IV devices that include transceivers must use the ALTGX_RECONFIG IP Core to implementdynamic reconfiguration. The ALTGX_RECONFIG IP Core alway

Parameter Name Options DescriptionEnable FEC status ports On/Off When you turn this option the core includes therx_block_lock, rx_parity_good, rx_pari

ALTGX Parameter Name (Default Value) XAUI PHY Parameter Name CommentsAcceptable PPM threshold betweenreceiver CDR VCO and receiverinput reference cloc

Differences Between XAUI PHY Ports in Stratix IV and Stratix V DevicesThis section lists the differences between the top-level signals in Stratix IV G

Stratix IV GX Devices(20)Stratix V DevicesSignal Name Width Signal Name Widthcal_blk_powerdown — Not available —rx_syncstatus [2<n> -1:0] rx_syn

Differences Between PHY IP Core for PCIe PHY (PIPE) Parameters inStratix IV and Stratix V DevicesThis section lists the PHY IP Core for PCI Express PH

ALTGX Parameter Name (Default Value) CI Express PHY (PIPE)Parameter NameCommentsTrain receiver CDR from pll_inclk (false)Not available inMegaWizard In

Table 20-5: PCIe PHY (PIPE) Correspondence between Stratix IV GX Device and Stratix V Device SignalsStratix IV GX Device Signal Name(21)Stratix V GX D

Stratix IV GX Device Signal Name(21)Stratix V GX Device Signal Name Widthpipephydonestatus pipe_phystatus [<n>-1:0]pipestatus pipe_rxstatus [3&l

Stratix IV GX Device Signal Name(21)Stratix V GX Device Signal Name WidthNot availablephy_mgmt_clk_reset 1phy_mgmt_clk 1phy_mgmt_address [8:0]phy_mgmt

ALTGX Parameter Name (Default Value) Custom PHY Parameter NameWhat is the deserializer block width?SingleDoubleDeserializer block width: (22)AutoSingl

Differences Between Custom PHY Ports in Stratix IV and Stratix V DevicesThis section lists the differences between the top-level signals in Stratix IV

Speed Detection ParametersSelecting the speed detection option gives the PHY the ability to detect to link partners that support 1G/10GbE but have dis

ALTGX(23)Custom PHY Widthrx_freqlocked rx_is_lockedtodata [<n>-1:0]Transceiver Control and Status Signalsgxb_powerdown phy_mgmt_clk_reset —rx_da

Additional Information for the Transceiver PHYIP Core212015.01.19UG-01080SubscribeSend FeedbackThis section provides the revision history for the chap

Chapter DocumentVersionChanges Made1G/10Gbps EthernetPHY IP Core2.7 Made the following changes:• Updated the chapter to indicate new IP instantiation

Chapter DocumentVersionChanges MadeCustom PHY IP Core 2.7 Made the following changes:• Updated the chapter to indicate new IP instantiation flow using

Chapter DocumentVersionChanges MadeStratix V TransceiverNative PHY IP Core2.7 Made the following changes:• Updated the chapter to indicate new IP inst

Chapter DocumentVersionChanges MadeArria V GZTransceiver NativePHY IP Core2.7 Made the following changes:• Updated the chapter to indicate new IP inst

Chapter DocumentVersionChanges MadeTransceiver PHYReset Controller IPCore2.7 Made the following changes:• Updated the chapter to indicate new IP insta

Chapter DocumentVersionChanges MadeBackplane Ethernet10GBASE-KR PHY2.6Made the following changes:• Corrected an error in the description of pcs_mode_r

Chapter DocumentVersionChanges Made1G/10GbE EthernetPHY IP Core2.6Made the following changes:• Corrected an error in the description of pcs_mode_rc[5:

Chapter DocumentVersionChanges MadeDeterministicLatency PHY IP Core2.6Made the following changes:• Corrected the description of tx_datak signal in Tab

In this figure, the colors have the following meanings:• Green-Altera- Cores available Quartus II IP Library, including the 1G/10Gb Ethernet MAC, the

Chapter DocumentVersionChanges MadeArria V GZTransceiver NativePHY IP Core2.6Made the following changes:• Removed the description for rx_clklow and rx

Chapter DocumentVersionChanges MadeAnalog ParametersSet Using QSFAssignments2.6Made the following changes:• Corrected values for XCVR_REFCLK_PIN_TERMI

Chapter DocumentVersionChanges Made1G/10GbE EthernetPHY IP Core2.5 Made the following changes:• Corrected definition of gxmii_rx_d. This signal is syn

Chapter DocumentVersionChanges MadeStratix V TransceiverNative PHY IP Core2.5 Made the following changes:• Corrected Figure 12-4 showing the 10G PCS d

Chapter DocumentVersionChanges MadeTransceiver Reconfi‐guration ControllerIP Core Overview2.5 Made the following changes:• Updated table for "Dev

Date DocumentVersionChanges Made1G/10Gbps EthernetPHY IP Core2.4Backplane Ethernet10GBASE-KR PHYIP Core2.4 Added descriptions of FEC-related bits: C2[

Date DocumentVersionChanges MadeIntroductionApril 2013 2.1 Update to introduction. Renamed heading "Additional TransceiverPHYs" to "Non

Date DocumentVersionChanges MadeTransceiver Reconfiguration ControllerApril 2013 2.1 Rename table 16-13 to DFE Registers. Fix typo in Reconfig Addrcol

Date DocumentVersionChanges MadeMarch 2013 2.0 Made the following changes:• Improved the description of automatic speed detection.• Updated speed grad

Date DocumentVersionChanges MadeStratix V Native PHYMarch 2013 2.0 Updated definition of User external TX PLL to include informationon how to instanti

• An embedded processor mode to override the state-machine-based training algorithm. This modeallows an embedded processor to establish link data rate

Date DocumentVersionChanges MadeMarch 2013 2.0 Initial Release.Analog Parameters Set Using QSF AssignmentMarch 2013 2.0 Made the following changes.• C

Date DocumentVersionChanges MadeFebruary 2013 1.9• Reformatted.• Corrected definition of rx_data_ready. This signal is used andindicates that the PCS

Date DocumentVersionChanges MadeFebruary 2013 1.9• Reformatted.• Removed QPI signals from Figure showing Arria V Native PHYCommon Interfaces. These si

Date DocumentVersionChanges MadeNovember 2012 1.8• Expanded discussion of the Arria V, Arria V GZ, Cyclone V, andStratix V Transceiver Native PHY IP C

Date DocumentVersionChanges MadeNovember 2012 1.8• Added Gen3 support.• Added Arria V GZ support.• Added ×2 support.• Added discussion of link equaliz

Date DocumentVersionChanges MadeArria V Transceiver Native PHYNovember 2012 1.8• Added support for Standard datapath.• Added support for multiple PLLs

Date DocumentVersionChanges MadeNovember 2012 1.8• Created separate chapter for analog parameters that werepreviously listed in the individual transce

Date DocumentVersionChanges MadeJune 2012 1.7• Added the following QSF settings to all transceiver PHY: XCVR_TX_PRE_EMP_PRE_TAP_USER, XCVR_TX_PRE_EMP_

Date DocumentVersionChanges MadePHY IP Core for PCI Express (PIPE)June 2012 1.7• Added the following QSF settings to all transceiver PHY: XCVR_TX_PRE_

Date DocumentVersionChanges MadeJune 2012 1.7• Added the following QSF settings to all transceiver PHY: XCVR_TX_PRE_EMP_PRE_TAP_USER, XCVR_TX_PRE_EMP_

Figure 4-4: TX Equalization in Daisy-Chain ModeRXEncodeHandshakeAdaptTXdmi*dmi*dmi*dmo*dmo* Partner A Parter C Parter BEqDecodeRXEncodeHandshakeAdaptT

Date DocumentVersionChanges MadeJune 2012 1.7• DFE now automatically runs offset calibration and phaseinterpolator (PI) phase calibration at power on.

Date DocumentVersionChanges MadeLow Latency PHYFebruary 2012 1.5• Added register definitions for Low Latency PHY.Deterministic Latency PHYFebruary 201

Date DocumentVersionChanges MadeDecember 2011 1.4• Changed definition of phy_mgmt_clk_reset. This signal isactive high and level sensitive.CustomDecem

Date DocumentVersionChanges MadeDecember 2011 1.4• Added duty cycle distortion (DCD) signal integrity feature.• Added PLL and channel reconfiguration

Date DocumentVersionChanges MadeInterlaken Transceiver PHYNovember 2011 1.3• Added tx_sync_done signal which indicates that all lanes of TXdata are sy

Date DocumentVersionChanges MadeNovember 2011 1.3• Added MIF support to allow transceiver reconfiguration froma .mif file that may contain updates to

Date DocumentVersionChanges MadeMay 2011 1.2• Added simulation section.• Revised Figure 1–1 on page 1–1 to show the TransceiverReconfiguration Control

Date DocumentVersionChanges MadeMay 2011 1.2• Added details about the 0 ready latency for tx_ready.• Added PLL support to lane rate parameter descript

Date DocumentVersionChanges MadeMay 2011 1.2• Added presets for the 2.50 GIGE and 1.25GIGE protocols.• Moved dynamic reconfiguration for the transceiv

Date DocumentVersionChanges MadeMigrating from Stratix IV to Stratix VMay 2011 1.2• Added discussion of dynamic reconfiguration for Stratix IV andStra

Interfaces for Deterministic Latency PHY...11-15Data Interface

Auto negotiation with XAUI is not supported. Auto negotiation is run upon power up or if the autonegotiation module is reset.The following figures ill

Date DocumentVersionChanges MadeDecember 2010 1.1• • Added Stratix V support• Changed phy_mgmt_address from 16 to 9 bits.• Renamed management interfac

Date DocumentVersionChanges MadeDecember 2010 1.1• Added simulation support in ModelSim SE• Added PIPE low latency configuration option• Changed phy_m

Date DocumentVersionChanges MadeNovember 2010 1.1• Corrected address offsets in PMA Analog Registers. These arebyte offsets and should be: 0x00, 0x04,

• Channel number—specifies the requested channel• Mode—specifies 1G or 10G data modes or AN or LT modes for the corresponding channel2. Select a chann

Figure 4-7: FEC Functional Block DiagramPCSTransmitEncodeScrambleGearboxPCSReceiveDecodeDescrambleBlock SyncBER and SyncHeader MonitorFEC (2112,2080)

Figure 4-8: FEC Codeword Format64 Bit Payload Word 064 Bit Payload Word 464 Bit Payload Word 864 Bit Payload Word 1264 Bit Payload Word 1664 Bit Paylo

• FEC Block Synchronizer: The FEC block synchronizer achieves FEC block delineation by locking tocorrectly received FEC blocks. An algorithm with hyst

10BASE-KR PHY InterfacesFigure 4-10: 10GBASE-KR Top-Level Signalsxgmii_tx_dc[71:0]xgmii_tx_clkxgmii_rx_dc[71:0]xgmii_rx_clkgmii_tx_d[7:0]gmii_rx_d[7:0

Related InformationComponent Interface Tcl Reference10GBASE-KR PHY Clock and Reset InterfacesThis topic provides a block diagram of the 10GBASE-KR clo

Table 4-10: Clock and Reset SignalsSignal Name Direction Descriptionrx_recovered_clk Output The RX clock which is recovered from the receiveddata. You

• Transceiver Reconfiguration Controller IP Core Overview on page 16-110GBASE-KR PHY Data InterfacesThe following table describes the signals in the X

10GBASE-KR GMII Data Interfacegmii_rx_errOutput When asserted, indicates an error. May be assertedat any time during a frame transfer to indicate aner

Bit Reversal and Polarity Inversion...13-20Interfaces...

Signal Name SDR XGMII Signal Name Descriptionxgmii_tx_dc[52:45] xgmii_sdr_data[47:40] Lane 5 dataxgmii_tx_dc[53] xgmii_sdr_ctrl[5] Lane 5 controlxgmii

10GBASE-KR PHY Control and Status InterfacesThe 10GBASE-KR XGMII and GMII interface signals drive data to and from PHY.Table 4-14: Control and Status

Signal Name Direction Descriptionref_clk_1g input. The random error without a ratematch FIFO mode is:• +/- 1 ns at 1000 Mbps• +/- 5 ns at 100 Mbps• +/

Signal Name Direction Descriptionrx_latency_adj_10g[15:0] Output When you enable 1588, this signal outputs the realtime latency in XGMII clock cycles

Table 4-15: Daisy Chain Interface SignalsSignal Name Direction Descriptiondmi_mode_en Input When asserted, enable Daisy Chain mode.dmi_frame_lock Inpu

Table 4-16: Embedded Processor Interface SignalsSignal Name Direction Descriptionupi_mode_en Input When asserted, enables embedded processor mode.upi_

Signal Name Direction Descriptionreconfig_from_xcvr[(<n>46-1):0]Output Reconfiguration signals to the ReconfigurationDesign Example. <n> g

Signal Name Direction Descriptionpcs_mode_rc[5:0] Output Specifies the PCS mode for reconfig using 1-hotencoding. The following modes are defined:• 6&

Signal Name Direction Descriptionrxeq_done Input Link training requires RX equalization to becomplete. Tie this signal to 1 to indicate that RXequaliz

Notes:• Unless otherwise indicated, the default value of all registers is 0.• Writing to reserved or undefined register addresses may have undefined s

Simulation Support...15

WordAddrBit R/W Name Description18 RW Assert KR FECRequestWhen set to 1, indicates that the core is requesting the FECability. When this bit changes,

WordAddrBit R/W Name Description0xB4 31:0 RSC FEC UncorrectedBlocksCounts the number of uncorrectable FEC blocks. Resets to 0when read. Otherwise, it

WordAddrBit R/W Name Description3 RO AN ADV RemoteFaultWhen set to 1, fault information has been sent to the linkpartner. When 0, a fault has not occu

WordAddrBit R/W Name Description• [4:0]: Selector• [9:5]: Echoed nonce which are set by the state machine• [12:10]: Pause bits• [13]: Remote Fault bit

WordAddrBit R/W Name Description0xC5 15:0 RW User Next pagelowThe Auto-Negotiation TX state machine uses these bits if theAuto-Negotiation next pages

WordAddrBit R/W Name Description0xCB24:0RO AN LP ADV Tech_A[24:0]Received technology ability field bits of Clause 73Auto-Negotiation. The 10GBASE-KR P

WordAddrBit R/W Name Description7:4 RW main_step_cnt[3:0]Specifies the number of equalization steps for each main tapupdate. There are about 20 settin

WordAddrBit R/W Name Description22:20 RW rx_ctle_modeRX CTLE mode in the Link Training algorithm. The defaultvalue is 3'b000. The following encod

WordAddrBit R/W Name Description0xD20RO Link Trained -Receiver statusWhen set to 1, the receiver is trained and is ready to receivedata. When set to 0

WordAddrBit R/W Name Description19:10 RW ber_time_k_frames Specifies the number of thousands of training frames toexamine for bit errors on the link f