Altera Transceiver PHY IP Core Manual de usuario descargar pdf (Pagina 183)

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Interlaken PHY Register Interface and Register Descriptions

This section describes the register interface and register descriptions.

The Avalon-MM PHY management interface provides access to the Interlaken PCS and PMA registers,

resets, error handling, and serial loopback controls. You can use an embedded controller acting as an

Avalon-MM master to send read and write commands to this Avalon-MM slave interface.

Table 7-9: Avalon-MM PCS Management Interface

Signal Name Direction Description

phy_mgmt_clk Input

Avalon-MM clock input.

There is no frequency restriction for Stratix V devices;

however, if you plan to use the same clock for the PHY

management interface and transceiver reconfigura‐

tion, you must restrict the frequency range of phy_

mgmt_clk to 100–150 MHz to meet the specification

for the transceiver reconfiguration clock.

phy_mgmt_clk_reset Input

Global reset signal that resets the entire Interlaken

PHY. This signal is active high and level sensitive.

When the Interlaken PHY IP connects to the

Transceiver PHY Reconfiguration Controller IP Core,

the Transceiver PHY Reconfiguration Controller

mgmt_rst_reset signal must be simultaneously

asserted with the phy_mgmt_clk_reset signal to bring

the Frame Generators in the link into alignment. This

is a mandatory requirement. Failure to comply to this

requirement will result in excessive transmit lane-to-

lane skew in the Interlaken link.

phy_mgmt_addr[8:0] Input 9-bit Avalon-MM address.

phy_mgmt_writedata[31:0] Input Input data.

phy_mgmt_readdata[31:0] Output Output data.

phy_mgmt_write Input Write signal.

phy_mgmt_read Input Read signal.

phy_mgmt_waitrequest Output When asserted, indicates that the Avalon-MM slave

interface is unable to respond to a read or write

request. When asserted, control signals to the Avalon-

MM slave interface must remain constant.

The following table specifies the registers that you can access using the Avalon-MM PHY management

interface using word addresses and a 32-bit embedded processor. A single address space provides access

to all registers. Writing to reserved or undefined register addresses may have undefined side effects.

Note:

All undefined register bits are reserved.

7-16

Interlaken PHY Register Interface and Register Descriptions

UG-01080

2015.01.19

Altera Corporation

Interlaken PHY IP Core

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