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Table 4-6: Receiver Protocol Signals
Note: S = Indicates the number of streams; 4 for multi standard (up to 12G) mode and 1 for other modes.
Signal Width Direction Description
rx_std
3 Output Receiver video standard. Applicable for 3G-SDI, and multi
standard modes.
• SD-SDI = 000
• HD-SDI = 001
• 3G-SDI Level B = 010
• 3G-SDI Level A = 011
• 6G-SDI Level B = 100
• 6G-SDI Level A = 101
• 12G-SDI Level B = 110
• 12G-SDI Level A = 111
rx_std_in
3 Input Indicates the received video standard. Applicable for 3G-SDI,
dual standard, and triple standard modes only.
rx_clkin
1 Input Receiver protocol clock input. This signal must be driven by the
rx_clkout clock signal from the transceiver block.
Note: Not applicable for Arria 10 devices.
rx_rst_proto_in
1 Input Receiver protocol reset signal. This signal must be driven by the
rx_rst_proto_out reset signal from the transceiver block.
Note: Not applicable for Arria 10 devices.
rx_clkin_b
1 Input Receiver protocol clock input for link B. This signal must be
driven by the rx_clkout_b clock signal from the transceiver
block. For HD-SDI dual link configuration only.
Note: Not applicable for Arria 10 devices.
rx_rst_proto_in_
b
1 Input Receiver protocol reset signal for link B. This signal must be
driven by the rx_rst_proto_out_b reset signal from the
transceiver block. For HD-SDI dual link receiver protocol
configuration only.
Note: Not applicable for Arria 10 devices.
rx_dataout
20 Output Receiver parallel data out.
4-32
SDI II IP Core Signals
UG-01125
2015.05.04
Altera Corporation
SDI II IP Core Functional Description
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- SDI II IP Core User Guide 1
- Contents 2
- Altera Corporation 3
- Item Description 4
- SDI II IP Core Overview 6
- SMPTE372 Dual Link Support 7
- HD Dual-Link Receiver 9
- 3-GB Receiver 10
- SMPTE RP168 Switching Support 11
- Dynamic TX Clock Switching 12
- UG-01125 13
- 2015.05.04 13
- Resource Utilization 14
- Block Memory Bits 15
- Registers 15
- Secondary Logic 15
- Installation and Licensing 16
- Design Walkthrough 16
- Launching IP Catalog 17
- Parameterizing the IP Core 18
- Timing Violation 19
- Programming an FPGA Device 20
- Design Reference 20
- SDI II IP Core Parameters 21
- Parameter Value Description 22
- Design Examples 24
- Testbench 25
- Example Design 25
- Input Signal Connection 26
- Design Example 27
- Video Pattern Generator 30
- Send Feedback 30
- Related Information 31
- Interfaces 36
- Logical Channel Number 36
- Signal Width Directio 42
- Description 42
- Protocol 44
- TX PHY Management 45
- & PHY Adapter 45
- TX Protocol Transceiver 45
- Payload ID 45
- Transceiver 47
- Receiver 48
- RX Protocol 49
- RX PHY Management 49
- Management 50
- & PHY Adapter Transceiver 50
- PHY Adapter 52
- Submodules 56
- Insert/Check CRC 57
- Insert Payload ID 57
- Match TRS 59
- Scrambler 59
- TX Sample 60
- Clock Enable Generator 60
- RX Sample 61
- Step Process Description 62
- Detect Video Standard 63
- Detect 1 and 1/1.001 Rates 63
- Transceiver Controller 63
- Descrambler 64
- TRS Aligner 65
- OUTPUT DATA 66
- OUTPUT LN 66
- Sync Streams 67
- Convert SD Bits 68
- Insert Sync Bits 68
- Clocking Scheme 69
- SDI II IP Core Signals 69
- Additional Information 87
- Date Version Changes 88
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