Altera SDI II MegaCore Manual de usuario Pagina 39
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Signal Width Direction Description
xcvr_reconfig_rst 1 Input Reset signal for reconfiguration user logic.
This signal is active high and level sensitive.
This reset signal must share the same reset
source as reconfig_reset in the transceiver.
xcvr_reconfig_write 1 Output Write enable signal.
Connect this signal to reconfig_write in the
transceiver.
xcvr_reconfig_read 1 Output Read enable signal.
Connect this signal to reconfig_read in the
transceiver.
xcvr_reconfig_address 10 Output Reconfiguration address.
Connect this signal to reconfig_address in
the transceiver.
xcvr_reconfig_writedata 32 Output A 32-bit data write bus.
Connect this bus to reconfig_writedata in
the transceiver.
xcvr_reconfig_readdata 32 Input A 32-bit data read bus. This signal returns
valid data from the transceiver after a read
operation.
Connect this bus to reconfig_readdata in
the transceiver.
xcvr_reconfig_waitrequest 1 Input Status signal from the transceiver that
indicates that the Avalon-MM interface is
busy.
Connect this signal to reconfig_
waitrequest in the transceiver.
cdr_reconfig_sel 2 Input Signal to specify which data rate the CDR
should be configured to.
Connect this signal to rx_std in the SDI II
IP core.
cdr_reconfig_req 1 Input Request signal to start the CDR dynamic
reconfiguration.
Connect this signal to rx_sdi_start_
reconfig in the SDI II IP core.
cdr_reconfig_busy 1 Output Status signal that indicates that CDR reconfi‐
guration is taking place.
Connect this signal to rx_sdi_reconfig_
done in the SDI II IP core.
3-24
Transceiver Reconfiguration Controller Signals
UG-01125
2015.05.04
Altera Corporation
SDI II IP Core Getting Started
Send Feedback
- SDI II IP Core User Guide 1
- Contents 2
- Altera Corporation 3
- Item Description 4
- SDI II IP Core Overview 6
- SMPTE372 Dual Link Support 7
- HD Dual-Link Receiver 9
- 3-GB Receiver 10
- SMPTE RP168 Switching Support 11
- Dynamic TX Clock Switching 12
- UG-01125 13
- 2015.05.04 13
- Resource Utilization 14
- Block Memory Bits 15
- Registers 15
- Secondary Logic 15
- Installation and Licensing 16
- Design Walkthrough 16
- Launching IP Catalog 17
- Parameterizing the IP Core 18
- Timing Violation 19
- Programming an FPGA Device 20
- Design Reference 20
- SDI II IP Core Parameters 21
- Parameter Value Description 22
- Design Examples 24
- Testbench 25
- Example Design 25
- Input Signal Connection 26
- Design Example 27
- Video Pattern Generator 30
- Send Feedback 30
- Related Information 31
- Interfaces 36
- Logical Channel Number 36
- Signal Width Directio 42
- Description 42
- Protocol 44
- TX PHY Management 45
- & PHY Adapter 45
- TX Protocol Transceiver 45
- Payload ID 45
- Transceiver 47
- Receiver 48
- RX Protocol 49
- RX PHY Management 49
- Management 50
- & PHY Adapter Transceiver 50
- PHY Adapter 52
- Submodules 56
- Insert/Check CRC 57
- Insert Payload ID 57
- Match TRS 59
- Scrambler 59
- TX Sample 60
- Clock Enable Generator 60
- RX Sample 61
- Step Process Description 62
- Detect Video Standard 63
- Detect 1 and 1/1.001 Rates 63
- Transceiver Controller 63
- Descrambler 64
- TRS Aligner 65
- OUTPUT DATA 66
- OUTPUT LN 66
- Sync Streams 67
- Convert SD Bits 68
- Insert Sync Bits 68
- Clocking Scheme 69
- SDI II IP Core Signals 69
- Additional Information 87
- Date Version Changes 88
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