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Signal Width Direction Description
pattgen_patho
1 Input Set to 1 to generate pathological pattern.
pattgen_blank
1 Input Set to 1 to generate black signal.
pattgen_no_color
1 Input Set to 1 to generate bars with no color.
pattgen_sgmt_frame
1 Input Set to 1 to generate segmented frame picture for tx_
format:
• 0100: SMPTE274M 1080sF30
• 0101: SMPTE274M 1080sF25
Related Information
Video Pattern Generator on page 3-15
Transceiver Reconfiguration Controller Signals
Table 3-9: Transceiver Reconfiguration Controller Signals for Arria V, Cyclone V, and Stratix V Devices
Table below lists the input signals for the transceiver reconfiguration controller. The listed signals are exported at
the top level of the design example. Other signals—that are not exported—connects within the design example
entity.
Signal Width Direction Description
reconfig_clk
1
Input
Clock signal for the transceiver reconfigura‐
tion controller and reconfiguration
management/router. Refer to the transceiver
reconfiguration controller section in the
Altera Transceiver PHY IP User Guide for
information about the frequency range.
reconfig_rst
1
Input
Reset signal for the transceiver reconfigura‐
tion controller and reconfiguration
management/router. This signal is active high
and level sensitive.
Table 3-10: Transceiver Reconfiguration Controller Signals for Arria 10 Devices
The table below describes the signals available for the reconfiguration controller.
Signal Width Direction Description
xcvr_reconfig_clk 1 Input Clock signal for reconfiguration user logic.
This clock must share the same clock source
as reconfig_clk in the transceiver.
UG-01125
2015.05.04
Transceiver Reconfiguration Controller Signals
3-23
SDI II IP Core Getting Started
Altera Corporation
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- SDI II IP Core User Guide 1
- Contents 2
- Altera Corporation 3
- Item Description 4
- SDI II IP Core Overview 6
- SMPTE372 Dual Link Support 7
- HD Dual-Link Receiver 9
- 3-GB Receiver 10
- SMPTE RP168 Switching Support 11
- Dynamic TX Clock Switching 12
- UG-01125 13
- 2015.05.04 13
- Resource Utilization 14
- Block Memory Bits 15
- Registers 15
- Secondary Logic 15
- Installation and Licensing 16
- Design Walkthrough 16
- Launching IP Catalog 17
- Parameterizing the IP Core 18
- Timing Violation 19
- Programming an FPGA Device 20
- Design Reference 20
- SDI II IP Core Parameters 21
- Parameter Value Description 22
- Design Examples 24
- Testbench 25
- Example Design 25
- Input Signal Connection 26
- Design Example 27
- Video Pattern Generator 30
- Send Feedback 30
- Related Information 31
- Interfaces 36
- Logical Channel Number 36
- Signal Width Directio 42
- Description 42
- Protocol 44
- TX PHY Management 45
- & PHY Adapter 45
- TX Protocol Transceiver 45
- Payload ID 45
- Transceiver 47
- Receiver 48
- RX Protocol 49
- RX PHY Management 49
- Management 50
- & PHY Adapter Transceiver 50
- PHY Adapter 52
- Submodules 56
- Insert/Check CRC 57
- Insert Payload ID 57
- Match TRS 59
- Scrambler 59
- TX Sample 60
- Clock Enable Generator 60
- RX Sample 61
- Step Process Description 62
- Detect Video Standard 63
- Detect 1 and 1/1.001 Rates 63
- Transceiver Controller 63
- Descrambler 64
- TRS Aligner 65
- OUTPUT DATA 66
- OUTPUT LN 66
- Sync Streams 67
- Convert SD Bits 68
- Insert Sync Bits 68
- Clocking Scheme 69
- SDI II IP Core Signals 69
- Additional Information 87
- Date Version Changes 88
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