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Table 2-2: Dynamic Switching Behavior During a Handshaking Process
Case Description
1 The handshaking process attempts to switch to select xcvr_refclk_alt. tx_clkout success‐
fully locks to xcvr_refclk_alt (148.35 MHz).
2 The handshaking process attempts to switch to select xcvr_refclk. tx_clkout successfully
locks to xcvr_refclk (148.5 MHz).
3 The handshaking process attempts to switch to select xcvr_refclk_alt. The switching fails
because ch1_{tx/du}_tx_pll_sel changes from 1 to 0 prior to the assertion of ch1_{tx/
du}_tx_start_reconfig. Therefore tx_clkout is still locked to xcvr_refclk (148.5MHz).
Resource Utilization
The tables below list the typical resource utilization for the SDI II IP core with the Quartus II software,
version 15.0.
Note:
The resource utilization data was obtained by using the most common configurations for each
video standard and from one specific family device.
Table 2-3: Resource Utilization for Each Video Standard (Arria V, Cyclone V, and Stratix V Devices)
Standard ALM Needed Primary Logic
Registers
Secondary Logic
Registers
Block Memory Bits
SD-SDI TX 95 126 10 0
SD-SDI RX 528 641 48 60
HD-SDI TX 141 159 10 0
HD-SDI RX 557 821 60 0
HD Dual Link TX 447 478 43 0
HD Dual Link RX 1,305 1,897 155 4,608
3G-SDI TX 444 414 12 0
3G-SDI RX 826 1307 125 0
Dual Rate TX 242 237 4 0
Dual Rate RX 924 1,209 84 0
Triple Rate TX 496 528 8 0
Triple Rate RX 1,064 1,583 98 0
Table 2-4: Resource Utilization for Each Video Standard (Arria 10 Devices)
Standard ALM Needed Primary Logic
Registers
Secondary Logic
Registers
Block Memory Bits
HD-SDI TX 106 124 23 0
HD-SDI RX 523 765 66 0
UG-01125
2015.05.04
Resource Utilization
2-9
SDI II IP Core Overview
Altera Corporation
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- SDI II IP Core User Guide 1
- Contents 2
- Altera Corporation 3
- Item Description 4
- SDI II IP Core Overview 6
- SMPTE372 Dual Link Support 7
- HD Dual-Link Receiver 9
- 3-GB Receiver 10
- SMPTE RP168 Switching Support 11
- Dynamic TX Clock Switching 12
- UG-01125 13
- 2015.05.04 13
- Resource Utilization 14
- Block Memory Bits 15
- Registers 15
- Secondary Logic 15
- Installation and Licensing 16
- Design Walkthrough 16
- Launching IP Catalog 17
- Parameterizing the IP Core 18
- Timing Violation 19
- Programming an FPGA Device 20
- Design Reference 20
- SDI II IP Core Parameters 21
- Parameter Value Description 22
- Design Examples 24
- Testbench 25
- Example Design 25
- Input Signal Connection 26
- Design Example 27
- Video Pattern Generator 30
- Send Feedback 30
- Related Information 31
- Interfaces 36
- Logical Channel Number 36
- Signal Width Directio 42
- Description 42
- Protocol 44
- TX PHY Management 45
- & PHY Adapter 45
- TX Protocol Transceiver 45
- Payload ID 45
- Transceiver 47
- Receiver 48
- RX Protocol 49
- RX PHY Management 49
- Management 50
- & PHY Adapter Transceiver 50
- PHY Adapter 52
- Submodules 56
- Insert/Check CRC 57
- Insert Payload ID 57
- Match TRS 59
- Scrambler 59
- TX Sample 60
- Clock Enable Generator 60
- RX Sample 61
- Step Process Description 62
- Detect Video Standard 63
- Detect 1 and 1/1.001 Rates 63
- Transceiver Controller 63
- Descrambler 64
- TRS Aligner 65
- OUTPUT DATA 66
- OUTPUT LN 66
- Sync Streams 67
- Convert SD Bits 68
- Insert Sync Bits 68
- Clocking Scheme 69
- SDI II IP Core Signals 69
- Additional Information 87
- Date Version Changes 88
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