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Figure 2-3: Example of 3G-SDI (Level B) to HD-SDI Dual Link Conversion
The figure shows the conversion of 3G-SDI (level B) data to two HD-SDI data streams.
3FFh(C2)
Demux
3FFh(C1)
3FFh(Y2)
3FFh(Y1)
000h(C2)
000h(C1)
000h(Y2)
000h(Y1)
XYZ(C2)
XYZ(C1)
XYZ(Y2)
XYZ(Y1)
LN0(C2)
LN0(C1)
LN0(Y2)
LN0(Y1)
LN1(C2)
LN1(C1)
LN1(Y2)
LN1(Y1)
3FFh(C1)
3FFh(Y1)
000h(C1)
000h(Y1)
XYZ(C1)
XYZ(Y1)
LN0(C1)
LN0(Y1)
LN1(C1)
LN1(Y1)
3FFh(C2)
3FFh(Y2)
000h(C2)
000h(Y2)
XYZ(C2)
XYZ(Y2)
LN0(C2)
LN0(Y2)
LN1(C2)
LN1(Y2)
000h(C1)
000h(Y1)
000h(C2)
000h(Y2)
3G-SDI Level B Interleaved Stream
Data Stream 1
HD-SDI Link A (10-bit)
HD-SDI Link B (10-bit)
Data Stream 2
Figure 2-4: Implementation of 3G-SDI (Level B) to HD-SDI Dual Link Conversion
The figure shows a block diagram of 3G-SDI (level B) to HD-SDI dual link conversion.
Transceiver
3-GB Signal
Protocol
3-GB
Demux
rxdata
rx_clkin_smpte372
(74.25 MHz or 74.175 MHz)
rx_dataout[19:0]
rdclk_3gb_div2 =
1H1L1H1L
xcvr_refclk (148.5 MHz or 148.35 MHz)
rx_clkout
(148.5 MHz or 148.35 MHz)
FIFO
rx_dataout_b[19:0]
rx_dataout[19:0]
rx_dataout_b[19:0]
wrreq
rxdata[19:0]
rx_trs
3-GB Receiver
rx_clkout
rx_trs
rxdata[19:10]
rxdata[9:0]
C1 C1 C1 C1Y1 Y1 Y1 Y1
C2 C2 C2 C2Y2 Y2 Y2 Y2
Y1 Y1 Y1 Y1
C1 C1 C1 C1
Y2 Y2 Y2 Y2
C2 C2 C2 C2
rx_clkin_smpte372
rx_dataout[19:10]
rx_dataout[9:0]
rx_clkdiv2
rx_dataout_b[19:10]
rx_dataout_b[9:0]
rx_clkout
rx_trs
UG-01125
2015.05.04
3G-SDI (Level B) to HD-SDI Dual Link Conversion
2-5
SDI II IP Core Overview
Altera Corporation
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- SDI II IP Core User Guide 1
- Contents 2
- Altera Corporation 3
- Item Description 4
- SDI II IP Core Overview 6
- SMPTE372 Dual Link Support 7
- HD Dual-Link Receiver 9
- 3-GB Receiver 10
- SMPTE RP168 Switching Support 11
- Dynamic TX Clock Switching 12
- UG-01125 13
- 2015.05.04 13
- Resource Utilization 14
- Block Memory Bits 15
- Registers 15
- Secondary Logic 15
- Installation and Licensing 16
- Design Walkthrough 16
- Launching IP Catalog 17
- Parameterizing the IP Core 18
- Timing Violation 19
- Programming an FPGA Device 20
- Design Reference 20
- SDI II IP Core Parameters 21
- Parameter Value Description 22
- Design Examples 24
- Testbench 25
- Example Design 25
- Input Signal Connection 26
- Design Example 27
- Video Pattern Generator 30
- Send Feedback 30
- Related Information 31
- Interfaces 36
- Logical Channel Number 36
- Signal Width Directio 42
- Description 42
- Protocol 44
- TX PHY Management 45
- & PHY Adapter 45
- TX Protocol Transceiver 45
- Payload ID 45
- Transceiver 47
- Receiver 48
- RX Protocol 49
- RX PHY Management 49
- Management 50
- & PHY Adapter Transceiver 50
- PHY Adapter 52
- Submodules 56
- Insert/Check CRC 57
- Insert Payload ID 57
- Match TRS 59
- Scrambler 59
- TX Sample 60
- Clock Enable Generator 60
- RX Sample 61
- Step Process Description 62
- Detect Video Standard 63
- Detect 1 and 1/1.001 Rates 63
- Transceiver Controller 63
- Descrambler 64
- TRS Aligner 65
- OUTPUT DATA 66
- OUTPUT LN 66
- Sync Streams 67
- Convert SD Bits 68
- Insert Sync Bits 68
- Clocking Scheme 69
- SDI II IP Core Signals 69
- Additional Information 87
- Date Version Changes 88
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