Altera SDI II MegaCore Manual de usuario Pagina 40
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Signal Width Direction Description
pll_sel 1 Input Signal to specify which TX PLL to use. This
signal must share the same source as pll_
select signal in the transceiver PHY reset
controller.
pll_sw_req 1 Input Request signal to start the PLL switching
dynamic reconfiguration.
Note: Do not assert this signal when
other reconfiguration signals are
busy, for example cdr_reconfig_
busy.
pll_busy 1 Output Status signal that indicates that the PLL
switching process is taking place.
external_avmm_master_req 1 Input Request signal from the external Avalon-MM
master. Tie this signal to 0 if you do not use
the external Avalon-MM master.
reconfig_write_from_ext_
avmm_master
1 Input Write enable signal. Connect this signal to the
write signal of the external Avalon-MM
master if you have one in your design.
reconfig_read_from_ext_
avmm_master
1 Input Read enable signal. Connect this signal to the
read signal of the external Avalon-MM
master if you have one in your design.
reconfig_address_from_ext_
avmm_master
10 Input Reconfiguration address. Connect this signal
to the reconfig address bus of the external
Avalon-MM master if you have one in your
design.
reconfig_writedata_from_
ext_avmm_master
32 Input A 32-bit data write bus. Connect this bus to
the reconfig data write bus of the
external Avalon-MM master if you have one
in your design.
reconfig_readdata_from_ext_
avmm_master
32 Output A 32-bit data read bus. Connect this bus to
the reconfig data read bus of the external
Avalon-MM master if you have one in your
design.
reconfig_waitrequest_from_
ext_avmm_master
1 Output
Status signal that indicates that the Avalon-
MM is busy. Connect this signal to the
waitrequest signal of the external Avalon-
MM master if you have one in your design.
Note: Do not issue any Avalon
commands when this signal is
high.
UG-01125
2015.05.04
Transceiver Reconfiguration Controller Signals
3-25
SDI II IP Core Getting Started
Altera Corporation
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- SDI II IP Core User Guide 1
- Contents 2
- Altera Corporation 3
- Item Description 4
- SDI II IP Core Overview 6
- SMPTE372 Dual Link Support 7
- HD Dual-Link Receiver 9
- 3-GB Receiver 10
- SMPTE RP168 Switching Support 11
- Dynamic TX Clock Switching 12
- UG-01125 13
- 2015.05.04 13
- Resource Utilization 14
- Block Memory Bits 15
- Registers 15
- Secondary Logic 15
- Installation and Licensing 16
- Design Walkthrough 16
- Launching IP Catalog 17
- Parameterizing the IP Core 18
- Timing Violation 19
- Programming an FPGA Device 20
- Design Reference 20
- SDI II IP Core Parameters 21
- Parameter Value Description 22
- Design Examples 24
- Testbench 25
- Example Design 25
- Input Signal Connection 26
- Design Example 27
- Video Pattern Generator 30
- Send Feedback 30
- Related Information 31
- Interfaces 36
- Logical Channel Number 36
- Signal Width Directio 42
- Description 42
- Protocol 44
- TX PHY Management 45
- & PHY Adapter 45
- TX Protocol Transceiver 45
- Payload ID 45
- Transceiver 47
- Receiver 48
- RX Protocol 49
- RX PHY Management 49
- Management 50
- & PHY Adapter Transceiver 50
- PHY Adapter 52
- Submodules 56
- Insert/Check CRC 57
- Insert Payload ID 57
- Match TRS 59
- Scrambler 59
- TX Sample 60
- Clock Enable Generator 60
- RX Sample 61
- Step Process Description 62
- Detect Video Standard 63
- Detect 1 and 1/1.001 Rates 63
- Transceiver Controller 63
- Descrambler 64
- TRS Aligner 65
- OUTPUT DATA 66
- OUTPUT LN 66
- Sync Streams 67
- Convert SD Bits 68
- Insert Sync Bits 68
- Clocking Scheme 69
- SDI II IP Core Signals 69
- Additional Information 87
- Date Version Changes 88
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