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TX Sample
The TX sample submodule is a transmit oversampling block. It repeats each bit of the input word a given
number of times and constructs the output words.
This submodule relies on the fact that the input data is only valid on 1/x of the clock cycles, where x is the
oversampling factor. Both the input and output words are clocked from the same clock domain.
Table 4-2: Oversampling Requirement
The table below lists the number of times oversampling is required for the different video standards.
SD-SDI SD-SDI HD-SDI Dual Rate Triple Rate Multi Rate
SD-SDI 11 11 11 11 44
HD-SDI — 2 2 2 8
3G-SDI — — — — 4
6G-SDI — — — — 2
12G-SDI — — — — —
Clock Enable Generator
The clock enable generator is a simple logic that generates a clock enable signal.
The clock enable signal serves as a data valid signal, tx_datain_valid for the incoming video data signal,
tx_datain. The video data signal is based on the incoming video standard signal, tx_std. The transmit
parallel clock, tx_pclk, can be a single frequency of either 148.5 MHz or 148.35 MHz.
The clock enable generator generates a clock signal in the following conditions:
• If the tx_datain signal is SD—generate a tx_datain_valid pulse every 5th and 11th clock cycle of
the tx_pclk domain.
• If the tx_datain signal is HD—generate a tx_datain_valid pulse every other clock cycle of the
tx_pclk domain.
• If the tx_datain signal is neither SD nor HD—the tx_datain_valid pulse remains high for 3G, 6G,
or 12G.
4-18
TX Sample
UG-01125
2015.05.04
Altera Corporation
SDI II IP Core Functional Description
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- SDI II IP Core User Guide 1
- Contents 2
- Altera Corporation 3
- Item Description 4
- SDI II IP Core Overview 6
- SMPTE372 Dual Link Support 7
- HD Dual-Link Receiver 9
- 3-GB Receiver 10
- SMPTE RP168 Switching Support 11
- Dynamic TX Clock Switching 12
- UG-01125 13
- 2015.05.04 13
- Resource Utilization 14
- Block Memory Bits 15
- Registers 15
- Secondary Logic 15
- Installation and Licensing 16
- Design Walkthrough 16
- Launching IP Catalog 17
- Parameterizing the IP Core 18
- Timing Violation 19
- Programming an FPGA Device 20
- Design Reference 20
- SDI II IP Core Parameters 21
- Parameter Value Description 22
- Design Examples 24
- Testbench 25
- Example Design 25
- Input Signal Connection 26
- Design Example 27
- Video Pattern Generator 30
- Send Feedback 30
- Related Information 31
- Interfaces 36
- Logical Channel Number 36
- Signal Width Directio 42
- Description 42
- Protocol 44
- TX PHY Management 45
- & PHY Adapter 45
- TX Protocol Transceiver 45
- Payload ID 45
- Transceiver 47
- Receiver 48
- RX Protocol 49
- RX PHY Management 49
- Management 50
- & PHY Adapter Transceiver 50
- PHY Adapter 52
- Submodules 56
- Insert/Check CRC 57
- Insert Payload ID 57
- Match TRS 59
- Scrambler 59
- TX Sample 60
- Clock Enable Generator 60
- RX Sample 61
- Step Process Description 62
- Detect Video Standard 63
- Detect 1 and 1/1.001 Rates 63
- Transceiver Controller 63
- Descrambler 64
- TRS Aligner 65
- OUTPUT DATA 66
- OUTPUT LN 66
- Sync Streams 67
- Convert SD Bits 68
- Insert Sync Bits 68
- Clocking Scheme 69
- SDI II IP Core Signals 69
- Additional Information 87
- Date Version Changes 88
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