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Signal Width Direction Description
tx_datain
20S Input User-supplied transmitter parallel data.
• SD-SDI = bits 19:10 unused; bits 9:0 C, Y, Cr, Y multiplex
• HD-SDI = bits 19:10 Y; bits 9:0 C
• HD-SDI dual link = bits 19:10 Y link A, bits 9:0 C link A
• 3G-SDI Level A = bits 19:10 Y; bits 9:0 C
• 3G-SDI Level B = bits 19:10 C, Y multiplex (link A); bits 9:0
C, Y multiplex (link B)
• Dual standard = bits 19:10 Y; bits 9:0 C
• Triple standard = bits 19:10 Y; bits 9:0 C
• Multi standard (up to 12G) = bits 79:70 Y of stream 3; bits
69:60 C of stream 3; bits 59:50 Y of stream 2; bits 49:40 C of
stream 2; bits 39:30 Y of stream 1; bits 29:20 C of stream 1;
bits 19:10 Y of stream 0; bits 9:0 C of stream 0
tx_datain_valid
1 Input Transmitter parallel data valid. The timing (H: High, L: Low)
must be synchronous to tx_pclk clock domain and have the
following settings:
• SD-SDI = 1H 4L 1H 5L
• HD-SDI = H
• 3G-SDI = H
• HD-SDI Dual Link = H
• Dual standard = SD (1H 4L 1H 5L); HD (1H 1L)
• Triple standard = SD (1H 4L 1H 5L); HD (1H 1L); 3G (H)
• Multi standard (up to 12G) = SD (1H 4L 1H 5L); HD (1H 1L);
3G/6G/12G (H)
Otherwise, this signal can be driven by the tx_dataout_valid
signal for SD-SDI, and multi standard modes.
tx_trs
1 Input Transmitter TRS input. For use in LN, CRC, or payload ID
insertion. Assert this signal on first word of both EAV and SAV
TRSs.
tx_ln_b
11S Input Transmitter line number for link B. For use in 3G-SDI, HD-SDI
dual link, triple standard, and multi standard (up to 12G) line
number insertion.
tx_datain_b
20 Input User-supplied transmitter parallel data for link B. Applicable for
HD-SDI dual link mode only.
• HD-SDI dual link = bits 19:10 Y link B, bits 9:0 C link B
tx_datain_valid_
b
1 Input Transmitter parallel data valid for link B. Applicable for HD-SDI
dual link mode only.
• HD-SDI dual link = H
UG-01125
2015.05.04
SDI II IP Core Signals
4-29
SDI II IP Core Functional Description
Altera Corporation
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- SDI II IP Core User Guide 1
- Contents 2
- Altera Corporation 3
- Item Description 4
- SDI II IP Core Overview 6
- SMPTE372 Dual Link Support 7
- HD Dual-Link Receiver 9
- 3-GB Receiver 10
- SMPTE RP168 Switching Support 11
- Dynamic TX Clock Switching 12
- UG-01125 13
- 2015.05.04 13
- Resource Utilization 14
- Block Memory Bits 15
- Registers 15
- Secondary Logic 15
- Installation and Licensing 16
- Design Walkthrough 16
- Launching IP Catalog 17
- Parameterizing the IP Core 18
- Timing Violation 19
- Programming an FPGA Device 20
- Design Reference 20
- SDI II IP Core Parameters 21
- Parameter Value Description 22
- Design Examples 24
- Testbench 25
- Example Design 25
- Input Signal Connection 26
- Design Example 27
- Video Pattern Generator 30
- Send Feedback 30
- Related Information 31
- Interfaces 36
- Logical Channel Number 36
- Signal Width Directio 42
- Description 42
- Protocol 44
- TX PHY Management 45
- & PHY Adapter 45
- TX Protocol Transceiver 45
- Payload ID 45
- Transceiver 47
- Receiver 48
- RX Protocol 49
- RX PHY Management 49
- Management 50
- & PHY Adapter Transceiver 50
- PHY Adapter 52
- Submodules 56
- Insert/Check CRC 57
- Insert Payload ID 57
- Match TRS 59
- Scrambler 59
- TX Sample 60
- Clock Enable Generator 60
- RX Sample 61
- Step Process Description 62
- Detect Video Standard 63
- Detect 1 and 1/1.001 Rates 63
- Transceiver Controller 63
- Descrambler 64
- TRS Aligner 65
- OUTPUT DATA 66
- OUTPUT LN 66
- Sync Streams 67
- Convert SD Bits 68
- Insert Sync Bits 68
- Clocking Scheme 69
- SDI II IP Core Signals 69
- Additional Information 87
- Date Version Changes 88
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