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Item Description
Features • 20-bit interface support for SD-SDI
• Multiple SDI standards and video formats
• Payload identification packet insertion and extraction
• Clock enable generator
• Video rate detection
• Cyclical redundancy check (CRC) encoding and decoding
(except SD)
• Line number (LN) insertion and extraction (except SD)
• Word scrambling and descrambling
• Word alignment
• Framing and extraction of video timing signals
• Dual link data stream synchronization (except SD)
• Transceiver dynamic reconfiguration
• RP168 support for synchronous video switching
• Dynamic TX clock switching
• OpenCore Plus evaluation
• SMPTE425M level A support (direct source image formatting)
• SMPTE425M level B support (dual link mapping)
Application • Digital video equipment
• Mixing and recording equipment
Device Family
Support
Arria
®
10 (preliminary), Arria V GX, Arria V GZ, Cyclone
®
V,
and Stratix
®
V FPGA device families.
Refer to the device support table and What’s New in Altera page of
the Altera website for detailed information.
Design Tools • IP Catalog in the Quartus II software for design creation and
compilation
• ModelSim
®
-Altera, Riviera-Pro, and VCS/VCS MX software
for design simulation or synthesis
Related Information
• Altera Software Installation and Licensing
• What's New in Altera IP
1-2
SDI II IP Core Quick Reference
UG-01125
2015.05.04
Altera Corporation
SDI II IP Core Quick Reference
Send Feedback
- SDI II IP Core User Guide 1
- Contents 2
- Altera Corporation 3
- Item Description 4
- SDI II IP Core Overview 6
- SMPTE372 Dual Link Support 7
- HD Dual-Link Receiver 9
- 3-GB Receiver 10
- SMPTE RP168 Switching Support 11
- Dynamic TX Clock Switching 12
- UG-01125 13
- 2015.05.04 13
- Resource Utilization 14
- Block Memory Bits 15
- Registers 15
- Secondary Logic 15
- Installation and Licensing 16
- Design Walkthrough 16
- Launching IP Catalog 17
- Parameterizing the IP Core 18
- Timing Violation 19
- Programming an FPGA Device 20
- Design Reference 20
- SDI II IP Core Parameters 21
- Parameter Value Description 22
- Design Examples 24
- Testbench 25
- Example Design 25
- Input Signal Connection 26
- Design Example 27
- Video Pattern Generator 30
- Send Feedback 30
- Related Information 31
- Interfaces 36
- Logical Channel Number 36
- Signal Width Directio 42
- Description 42
- Protocol 44
- TX PHY Management 45
- & PHY Adapter 45
- TX Protocol Transceiver 45
- Payload ID 45
- Transceiver 47
- Receiver 48
- RX Protocol 49
- RX PHY Management 49
- Management 50
- & PHY Adapter Transceiver 50
- PHY Adapter 52
- Submodules 56
- Insert/Check CRC 57
- Insert Payload ID 57
- Match TRS 59
- Scrambler 59
- TX Sample 60
- Clock Enable Generator 60
- RX Sample 61
- Step Process Description 62
- Detect Video Standard 63
- Detect 1 and 1/1.001 Rates 63
- Transceiver Controller 63
- Descrambler 64
- TRS Aligner 65
- OUTPUT DATA 66
- OUTPUT LN 66
- Sync Streams 67
- Convert SD Bits 68
- Insert Sync Bits 68
- Clocking Scheme 69
- SDI II IP Core Signals 69
- Additional Information 87
- Date Version Changes 88
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