Altera SDI II MegaCore Manual de usuario Pagina 2
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Contents
SDI II IP Core Quick Reference..........................................................................1-1
SDI II IP Core Overview......................................................................................2-1
General Description.....................................................................................................................................2-1
SMPTE372 Dual Link Support.......................................................................................................2-2
SMPTE RP168 Switching Support.................................................................................................2-6
SD 20-Bit Interface for Dual/Triple Standard..............................................................................2-6
Dynamic TX Clock Switching........................................................................................................2-7
Resource Utilization.................................................................................................................................... 2-9
SDI II IP Core Getting Started............................................................................3-1
Installation and Licensing...........................................................................................................................3-1
Design Walkthrough................................................................................................................................... 3-1
Creating a New Quartus II Project................................................................................................3-2
Launching IP Catalog......................................................................................................................3-2
Parameterizing the IP Core............................................................................................................ 3-3
Generating a Design Example and Simulation Testbench.........................................................3-3
Simulating the SDI II IP Core Design...........................................................................................3-3
Compiling the SDI II IP Core Design.......................................................................................................3-4
Programming an FPGA Device................................................................................................................. 3-5
Design Reference..........................................................................................................................................3-5
SDI II IP Core Parameters..............................................................................................................3-6
SDI II IP Core Component Files....................................................................................................3-9
Design Examples..............................................................................................................................3-9
Video Pattern Generator Signals................................................................................................. 3-22
Transceiver Reconfiguration Controller Signals.......................................................................3-23
Reconfiguration Management Parameters.................................................................................3-26
Reconfiguration Router Signals...................................................................................................3-27
SDI II IP Core Functional Description...............................................................4-1
Protocol......................................................................................................................................................... 4-2
Transmitter.......................................................................................................................................4-2
Receiver............................................................................................................................................. 4-6
Transceiver..................................................................................................................................................4-12
Submodules.................................................................................................................................................4-14
Insert Line.......................................................................................................................................4-14
Insert/Check CRC..........................................................................................................................4-15
Insert Payload ID........................................................................................................................... 4-15
Match TRS...................................................................................................................................... 4-17
Scrambler........................................................................................................................................ 4-17
TOC-2
Altera Corporation
- SDI II IP Core User Guide 1
- Contents 2
- Altera Corporation 3
- Item Description 4
- SDI II IP Core Overview 6
- SMPTE372 Dual Link Support 7
- HD Dual-Link Receiver 9
- 3-GB Receiver 10
- SMPTE RP168 Switching Support 11
- Dynamic TX Clock Switching 12
- UG-01125 13
- 2015.05.04 13
- Resource Utilization 14
- Block Memory Bits 15
- Registers 15
- Secondary Logic 15
- Installation and Licensing 16
- Design Walkthrough 16
- Launching IP Catalog 17
- Parameterizing the IP Core 18
- Timing Violation 19
- Programming an FPGA Device 20
- Design Reference 20
- SDI II IP Core Parameters 21
- Parameter Value Description 22
- Design Examples 24
- Testbench 25
- Example Design 25
- Input Signal Connection 26
- Design Example 27
- Video Pattern Generator 30
- Send Feedback 30
- Related Information 31
- Interfaces 36
- Logical Channel Number 36
- Signal Width Directio 42
- Description 42
- Protocol 44
- TX PHY Management 45
- & PHY Adapter 45
- TX Protocol Transceiver 45
- Payload ID 45
- Transceiver 47
- Receiver 48
- RX Protocol 49
- RX PHY Management 49
- Management 50
- & PHY Adapter Transceiver 50
- PHY Adapter 52
- Submodules 56
- Insert/Check CRC 57
- Insert Payload ID 57
- Match TRS 59
- Scrambler 59
- TX Sample 60
- Clock Enable Generator 60
- RX Sample 61
- Step Process Description 62
- Detect Video Standard 63
- Detect 1 and 1/1.001 Rates 63
- Transceiver Controller 63
- Descrambler 64
- TRS Aligner 65
- OUTPUT DATA 66
- OUTPUT LN 66
- Sync Streams 67
- Convert SD Bits 68
- Insert Sync Bits 68
- Clocking Scheme 69
- SDI II IP Core Signals 69
- Additional Information 87
- Date Version Changes 88
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