Altera V-Series Avalon-MM DMA Manual de usuario Pagina 96
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Byte Offset
Register Dir Description
14'h0018 cfg_sec_ctrl[15:0]
O Secondary bus Control and Status register of the
PCI-Express capability. This register is only
available in Root Port mode.
14'h001C cfg_secbus[7:0]
O Secondary bus number. Available in Root Port
mode.
14'h0020 cfg_subbus[7:0]
O Subordinate bus number. Available in Root Port
mode.
14'h0024 cfg_msi_addr_low[31:0]
O cfg_msi_add[31:0] is the MSI message address.
14'h0028 cfg_msi_addr_hi[63:32]
O cfg_msi_add[63:32] is the MSI upper message
address.
14'h002C cfg_io_bas[19:0]
O The IO base register of the Type1 Configuration
Space. This register is only available in Root Port
mode.
14'h0030 cfg_io_lim[19:0]
O The IO limit register of the Type1 Configuration
Space. This register is only available in Root Port
mode.
14'h0034 cfg_np_bas[11:0]
O The non-prefetchable memory base register of the
Type1 Configuration Space. This register is only
available in Root Port mode.
14'h0038 cfg_np_lim[11:0]
O The non-prefetchable memory limit register of the
Type1 Configuration Space. This register is only
available in Root Port mode.
14'h003C cfg_pr_bas_low[31:0]
O The lower 32 bits of the prefetchable base register of
the Type1 Configuration Space. This register is only
available in Root Port mode.
14'h0040 cfg_pr_bas_hi[43:32]
O The upper 12 bits of the prefetchable base registers
of the Type1 Configuration Space. This register is
only available in Root Port mode.
14'h0044 cfg_pr_lim_low[31:0]
O The lower 32 bits of the prefetchable limit registers
of the Type1 Configuration Space. This register is
only available in Root Port mode.
UG-01154
2014.12.18
Control Register Access (CRA) Avalon-MM Slave Port
5-27
Registers
Altera Corporation
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- User Guide 1
- Features 3
- Interface 5
- Release Information 8
- Example Designs 9
- Debug Features 9
- IP Core Verification 9
- Related Information 10
- Altera Corporation 11
- Datasheet 11
- Send Feedback 11
- Parameter Value 17
- Directory Description 18
- Time TLP Type Payload 18
- TLP Header 18
- Creating a Quartus II Project 19
- Compiling the Design 20
- Parameter Settings 22
- Parameter Value Description 23
- Device Capabilities 28
- Error Reporting 28
- Link Capabilities 29
- MSI and MSI-X Capabilities 29
- Power Management 30
- PCIe Address Space Settings 31
- RX Master Module 36
- TX Slave Module 38
- Signal Name Directio 39
- Description 39
- Bits Name Description 41
- Clock Signals 45
- Signal Direction Description 46
- MSI Interrupts for Endpoints 51
- Serial Data Signals 53
- 9 Ch 18 Ch 54
- PIPE Interface Signals 64
- Test Signals 68
- Registers 70
- Altera-Defined VSEC Registers 77
- CvP Registers 78
- Bits Register Description 82
- Register Access Description 86
- Read DMA Example 91
- Byte Offset 95
- Register Dir Description 95
- Reset and Clocks 100
- Example Design 101
- Hard IP for PCI Express 101
- UG-01154 102
- 2014.12.18 102
- Clock Domains 104
- Data Rate Frequency 105
- Clock Summary 106
- Error Handling 107
- Physical Layer Errors 108
- Data Link Layer Errors 108
- Transaction Layer Errors 109
- Error Type Description 110
- Status Bit Conditions 112
- IP Core Architecture 114
- Hard IP for PCI Express 115
- Top-Level Interfaces 116
- Avalon-MM DMA Interface 116
- Clocks and Reset 116
- Transceiver Reconfiguration 116
- Interrupts 116
- Data Link Layer 117
- Physical Layer 119
- TX Packets 120
- Altera FPGA 122
- Qsys System 123
- Subscribe 125
- Address[31:2] 130
- Figure A-6: I/O Read Request 132
- Additional Information 136
- Date Version Changes Made 137
- How to Contact Altera 139
- Typographic Conventions 140
- Visual Cue Meaning 141
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