Altera V-Series Avalon-MM DMA Manual de usuario Pagina 130
- Pagina / 142
- Tabla de contenidos
- MARCADORES
Valorado. / 5. Basado en revisión del cliente
Transaction Layer Packet (TLP) Header Formats
A
2014.12.18
UG-01154
Subscribe
Send Feedback
The following figures show the header format for TLPs without a data payload.
Figure A-1: Memory Read Request, 32-Bit Addressing
Memory Read Request, 32-Bit Addressing
3+2+1+0+
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Byte 0 0 0 0 0 0 0 0 0 0
TC
0 0 0 0
TD EP Attr
0 0
Length
Byte 4
EB tsriFEB tsaLgaTDI retseuqeR
Byte 8
Address[31:2]
0 0
Byte 12 Reserved
Figure A-2: Memory Read Request, Locked 32-Bit Addressing
Memory Read Request, Locked 32-Bit Addressing
3+2+1+0+
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Byte 0 0 0 0 0 0 0 0 1 0 TC 0 0 0 0 TD EP Attr 0 0 Length
Byte 4
EB tsriFEB tsaLgaTDI retseuqeR
Byte 8
Address[31:2]
0 0
Byte 12 Reserved
©
2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
www.altera.com
101 Innovation Drive, San Jose, CA 95134
- User Guide 1
- Features 3
- Interface 5
- Release Information 8
- Example Designs 9
- Debug Features 9
- IP Core Verification 9
- Related Information 10
- Altera Corporation 11
- Datasheet 11
- Send Feedback 11
- Parameter Value 17
- Directory Description 18
- Time TLP Type Payload 18
- TLP Header 18
- Creating a Quartus II Project 19
- Compiling the Design 20
- Parameter Settings 22
- Parameter Value Description 23
- Device Capabilities 28
- Error Reporting 28
- Link Capabilities 29
- MSI and MSI-X Capabilities 29
- Power Management 30
- PCIe Address Space Settings 31
- RX Master Module 36
- TX Slave Module 38
- Signal Name Directio 39
- Description 39
- Bits Name Description 41
- Clock Signals 45
- Signal Direction Description 46
- MSI Interrupts for Endpoints 51
- Serial Data Signals 53
- 9 Ch 18 Ch 54
- PIPE Interface Signals 64
- Test Signals 68
- Registers 70
- Altera-Defined VSEC Registers 77
- CvP Registers 78
- Bits Register Description 82
- Register Access Description 86
- Read DMA Example 91
- Byte Offset 95
- Register Dir Description 95
- Reset and Clocks 100
- Example Design 101
- Hard IP for PCI Express 101
- UG-01154 102
- 2014.12.18 102
- Clock Domains 104
- Data Rate Frequency 105
- Clock Summary 106
- Error Handling 107
- Physical Layer Errors 108
- Data Link Layer Errors 108
- Transaction Layer Errors 109
- Error Type Description 110
- Status Bit Conditions 112
- IP Core Architecture 114
- Hard IP for PCI Express 115
- Top-Level Interfaces 116
- Avalon-MM DMA Interface 116
- Clocks and Reset 116
- Transceiver Reconfiguration 116
- Interrupts 116
- Data Link Layer 117
- Physical Layer 119
- TX Packets 120
- Altera FPGA 122
- Qsys System 123
- Subscribe 125
- Address[31:2] 130
- Figure A-6: I/O Read Request 132
- Additional Information 136
- Date Version Changes Made 137
- How to Contact Altera 139
- Typographic Conventions 140
- Visual Cue Meaning 141
Relacionado con productos y manuales para Instrumentos de medición Altera V-Series Avalon-MM DMA
Instrumentos de medición Altera 100G Development Kit, Stratix V GX Edition Manual de usuario
(76 paginas)
(76 paginas)
Instrumentos de medición Altera Arria II GX FPGA Development Board, 6G Edition Manual de usuario
(62 paginas)
(62 paginas)
Instrumentos de medición Altera Cyclone IV GX Transceiver Starter Board Manual de usuario
(40 paginas)
(40 paginas)
Instrumentos de medición Altera DSP Development Kit, Stratix V Edition Manual de usuario
(74 paginas)
(74 paginas)
Instrumentos de medición Altera Transceiver Signal Integrity Development Kit, Stra Manual de usuario
(42 paginas)
(42 paginas)
© 2020, manymanuals.es. Todos los derechos reservados | 0.038 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Comentarios a estos manuales