Altera V-Series Avalon-MM DMA Manual de usuario Pagina 51
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Signal Direction Description
Note that not all simulation models assert the Transaction Layer
error bit in conjunction with the Data Link Layer error bit.
The signal is not available for Arria V and Cyclone V devices.
Related Information
• Reset and Clocks on page 6-1
• Clocks on page 6-5
• PCI Express Card Electromechanical Specification 2.0
• Configuration via Protocol (CvP) Implementation in Altera FPGAs User Guide
MSI Interrupts for Endpoints
The MSI interrupt notifies the host when a DMA operation has completed. After the host receives this
interrupt, it can poll the DMA read or write status table to determine which entry or entries have the done
bit set. This mechanism allows host software to avoid continuous polling of the status table done bits.
Table 4-19: MSI Interrupt
Signal Direction Description
MSIIntfc_o[81:0]
Output This bus provides the following MSI address, data, and enabled
signals:
• MSIIntfc_o[81]: Master enable
• MSIIntfc_o[80}: MSI enable
• MSIIntfc_o[79:64]: MSI data
• MSIIntfc_o[63:0]: MSI address
MSIXIntfc_o[15:0]
Output Provides for system software control of MSI-X as defined in
Section 6.8.2.3 Message Control for MSI-X in the PCI Local Bus
Specification, Rev. 3.0. The following fields are defined:
• MSIXIntfc_o[15]: Enable
• MSIXIntfc_o[14]: Mask
• MSIXIntfc_o[13:11]: Reserved
• MSIXIntfc_o[10:0]: Table size
4-20
MSI Interrupts for Endpoints
UG-01154
2014.12.18
Altera Corporation
Interfaces and Signal Descriptions
Send Feedback
- User Guide 1
- Features 3
- Interface 5
- Release Information 8
- Example Designs 9
- Debug Features 9
- IP Core Verification 9
- Related Information 10
- Altera Corporation 11
- Datasheet 11
- Send Feedback 11
- Parameter Value 17
- Directory Description 18
- Time TLP Type Payload 18
- TLP Header 18
- Creating a Quartus II Project 19
- Compiling the Design 20
- Parameter Settings 22
- Parameter Value Description 23
- Device Capabilities 28
- Error Reporting 28
- Link Capabilities 29
- MSI and MSI-X Capabilities 29
- Power Management 30
- PCIe Address Space Settings 31
- RX Master Module 36
- TX Slave Module 38
- Signal Name Directio 39
- Description 39
- Bits Name Description 41
- Clock Signals 45
- Signal Direction Description 46
- MSI Interrupts for Endpoints 51
- Serial Data Signals 53
- 9 Ch 18 Ch 54
- PIPE Interface Signals 64
- Test Signals 68
- Registers 70
- Altera-Defined VSEC Registers 77
- CvP Registers 78
- Bits Register Description 82
- Register Access Description 86
- Read DMA Example 91
- Byte Offset 95
- Register Dir Description 95
- Reset and Clocks 100
- Example Design 101
- Hard IP for PCI Express 101
- UG-01154 102
- 2014.12.18 102
- Clock Domains 104
- Data Rate Frequency 105
- Clock Summary 106
- Error Handling 107
- Physical Layer Errors 108
- Data Link Layer Errors 108
- Transaction Layer Errors 109
- Error Type Description 110
- Status Bit Conditions 112
- IP Core Architecture 114
- Hard IP for PCI Express 115
- Top-Level Interfaces 116
- Avalon-MM DMA Interface 116
- Clocks and Reset 116
- Transceiver Reconfiguration 116
- Interrupts 116
- Data Link Layer 117
- Physical Layer 119
- TX Packets 120
- Altera FPGA 122
- Qsys System 123
- Subscribe 125
- Address[31:2] 130
- Figure A-6: I/O Read Request 132
- Additional Information 136
- Date Version Changes Made 137
- How to Contact Altera 139
- Typographic Conventions 140
- Visual Cue Meaning 141
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