Altera V-Series Avalon-MM DMA Manual de usuario Pagina 37
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If burst mode is not enabled, the RX Master module only supports 32-bit read or write request. All other
requests received from the PCIe link are considered a violation of this device’s programming model, and
are therefore handled with the PCIe Completer Abort status. You can enable burst mode for BAR2 using
32-bit addressing or BAR2 and BAR3 using 64-bit addressing. When enabled, the module supports
dword, burst read or write requests. When the Descriptor Controller is internally instantiated, the RX
Master for BAR0 is used internally and not available for other uses.
Table 4-3: RX Master Control Interface Ports for BAR Access
Each BAR has one corresponding RX Master Control interface. In this table, <n> is the BAR number.
Signal Name Direction Description
RxmRead_<n>_o
Output When asserted, indicates an Avalon-MM read request.
RxmWrite_<n>_o
Output When asserted, indicates an Avalon-MM write request.
RxmAddress_<n>_o[<w>-
1:0]
Output Specifies the Avalon-MM byte address. Because all addresses are
byte addresses, the meaningful bits of this address are [<w>-1:2].
Bits 1 and 0 have a value of 0. <w> can be 32 or 64.
RxmBurstCount_<n>_
o[5:0]
Output Specifies the burst count in dwords (32 bits). This optional signal
is available for BAR2 when you turn on Enable burst capabili‐
ties for RXM BAR2 ports.
RxmByteEnable_<n>_
o[<w>:0]
Output Specifies the valid bytes of data to be written. <w> has the
following values:
• 4: for the non-bursting RX Master
• 32: for the bursting 128-bit Avalon-MM interface
• 64: for the bursting 256-bit Avalon-MM interface
RxmDataWrite_<n>_
o[<w>:0]
Output Specifies the Avalon-MM write data. <w> has the following
values:
• 32: for the non-bursting RX Master
• 128: for the bursting 128-bit Avalon-MM interface
• 256: for the bursting 256-bit Avalon-MM interface
RxmReadData_<n>_i[<w>
:0]
Input Specifies the Avalon-MM read data. <w> has the following
values:
• 32: for the non-bursting RX Master
• 128: for the bursting 128-bit Avalon-MM interface
• 256: for the bursting 256-bit Avalon-MM interface
RxmReadDataValid_<n>_
i[31:0]
Input
When asserted, indicates that RxmReadData_i[31:0]is
valid.
RxmWaitRequest_<n>_i
Input When asserted indicates that the control register access Avalon-
MM slave port is not ready to respond.
4-6
RX Master Module
UG-01154
2014.12.18
Altera Corporation
Interfaces and Signal Descriptions
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- User Guide 1
- Features 3
- Interface 5
- Release Information 8
- Example Designs 9
- Debug Features 9
- IP Core Verification 9
- Related Information 10
- Altera Corporation 11
- Datasheet 11
- Send Feedback 11
- Parameter Value 17
- Directory Description 18
- Time TLP Type Payload 18
- TLP Header 18
- Creating a Quartus II Project 19
- Compiling the Design 20
- Parameter Settings 22
- Parameter Value Description 23
- Device Capabilities 28
- Error Reporting 28
- Link Capabilities 29
- MSI and MSI-X Capabilities 29
- Power Management 30
- PCIe Address Space Settings 31
- RX Master Module 36
- TX Slave Module 38
- Signal Name Directio 39
- Description 39
- Bits Name Description 41
- Clock Signals 45
- Signal Direction Description 46
- MSI Interrupts for Endpoints 51
- Serial Data Signals 53
- 9 Ch 18 Ch 54
- PIPE Interface Signals 64
- Test Signals 68
- Registers 70
- Altera-Defined VSEC Registers 77
- CvP Registers 78
- Bits Register Description 82
- Register Access Description 86
- Read DMA Example 91
- Byte Offset 95
- Register Dir Description 95
- Reset and Clocks 100
- Example Design 101
- Hard IP for PCI Express 101
- UG-01154 102
- 2014.12.18 102
- Clock Domains 104
- Data Rate Frequency 105
- Clock Summary 106
- Error Handling 107
- Physical Layer Errors 108
- Data Link Layer Errors 108
- Transaction Layer Errors 109
- Error Type Description 110
- Status Bit Conditions 112
- IP Core Architecture 114
- Hard IP for PCI Express 115
- Top-Level Interfaces 116
- Avalon-MM DMA Interface 116
- Clocks and Reset 116
- Transceiver Reconfiguration 116
- Interrupts 116
- Data Link Layer 117
- Physical Layer 119
- TX Packets 120
- Altera FPGA 122
- Qsys System 123
- Subscribe 125
- Address[31:2] 130
- Figure A-6: I/O Read Request 132
- Additional Information 136
- Date Version Changes Made 137
- How to Contact Altera 139
- Typographic Conventions 140
- Visual Cue Meaning 141
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