Altera V-Series Avalon-MM DMA Manual de usuario Pagina 90
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Read DMA and Write DMA Descriptor Format
Read and write descriptors are stored in separate descriptor tables. Each table can store up to 128 descrip‐
tors. Each descriptor is 8 dwords, or 32 bytes. The Read DMA and Write DMA descriptor tables start at a
0x200 byte offset from the addresses programmed into the RC Read Descriptor Base and RC Write
Descriptor Base address registers.
Table 5-17: Read Descriptor Format
Address
Offset
Register Name
Description
0x00
RD_RC_LOW_SRC_ADDR
Lower dword of the read DMA source address. Specifies
the address in Root Complex memory from which the
Read DMA fetches data.
0x04
RD_RC_HIGH_SRC_ADDR
Upper dword of the read DMA source address. Specifies
the address in Root Complex memory from which the
Read DMA fetches data.
0x08
RD_CTLR_LOW_DEST_ADDR
Lower dword of the read DMA destination address.
Specifies the address in the Avalon-MM domain to
which the Read DMA writes data.
0x0C
RD_CTRL_HIGH_DEST_ADDR
Upper dword of the read DMA destination address.
Specifies the address in the Avalon-MM domain to
which the Read DMA writes data.
0x10 CONTROL Specifies the following information:
• [31:25] Reserved must be 0.
• [24:18] ID. Specifies the Descriptor ID. Descriptor
ID 0 is at the beginning of the table. Descriptor ID
is at the end of the table.
• [17:0] SIZE. The transfer size in dwords. Must be
non-zero. The maximum transfer size in 1 MBytes -
4 bytes.
0x14 -
0x1C
Reserved N/A
Table 5-18: Write Descriptor Format
Address
Offset
Register Name
Description
0x00
WR_RC_LOW_SRC_ADDR
Lower dword of the write DMA source address.
Specifies the address in the Avalon-MM domain from
which the Write DMA fetches data.
UG-01154
2014.12.18
Read DMA and Write DMA Descriptor Format
5-21
Registers
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- User Guide 1
- Features 3
- Interface 5
- Release Information 8
- Example Designs 9
- Debug Features 9
- IP Core Verification 9
- Related Information 10
- Altera Corporation 11
- Datasheet 11
- Send Feedback 11
- Parameter Value 17
- Directory Description 18
- Time TLP Type Payload 18
- TLP Header 18
- Creating a Quartus II Project 19
- Compiling the Design 20
- Parameter Settings 22
- Parameter Value Description 23
- Device Capabilities 28
- Error Reporting 28
- Link Capabilities 29
- MSI and MSI-X Capabilities 29
- Power Management 30
- PCIe Address Space Settings 31
- RX Master Module 36
- TX Slave Module 38
- Signal Name Directio 39
- Description 39
- Bits Name Description 41
- Clock Signals 45
- Signal Direction Description 46
- MSI Interrupts for Endpoints 51
- Serial Data Signals 53
- 9 Ch 18 Ch 54
- PIPE Interface Signals 64
- Test Signals 68
- Registers 70
- Altera-Defined VSEC Registers 77
- CvP Registers 78
- Bits Register Description 82
- Register Access Description 86
- Read DMA Example 91
- Byte Offset 95
- Register Dir Description 95
- Reset and Clocks 100
- Example Design 101
- Hard IP for PCI Express 101
- UG-01154 102
- 2014.12.18 102
- Clock Domains 104
- Data Rate Frequency 105
- Clock Summary 106
- Error Handling 107
- Physical Layer Errors 108
- Data Link Layer Errors 108
- Transaction Layer Errors 109
- Error Type Description 110
- Status Bit Conditions 112
- IP Core Architecture 114
- Hard IP for PCI Express 115
- Top-Level Interfaces 116
- Avalon-MM DMA Interface 116
- Clocks and Reset 116
- Transceiver Reconfiguration 116
- Interrupts 116
- Data Link Layer 117
- Physical Layer 119
- TX Packets 120
- Altera FPGA 122
- Qsys System 123
- Subscribe 125
- Address[31:2] 130
- Figure A-6: I/O Read Request 132
- Additional Information 136
- Date Version Changes Made 137
- How to Contact Altera 139
- Typographic Conventions 140
- Visual Cue Meaning 141
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