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Software Program for Simultaneous Read and Write DMA
Program the following steps to implement a simultaneous DMA transfer:
1. Allocate Root Port memory for the Read and Write DMA descriptor tables. Assume the table includes
up to 128, eight-dword descriptors and 128, one-dword status entries for a total of 1152 dwords. Total
memory for the Read and Write DMA descriptor tables is 2304 dwords.
2. Allocate Root Port memory and initialize it with data for the Read DMA to read.
3. Allocate Root Port memory for the Write DMA to write.
4. Create all the descriptors for the read DMA descriptor table. Assign the DMA Descriptor IDs
sequentially, starting with 0 to a maximum of 127. For the read DMA, the source address is the
memory space allocated in Step 2. The destination address is the Avalon-MM address that the Read
DMA module writes. Specify the DMA length in dwords. Each descriptor transfers contiguous
memory. Assuming a base address of 0, for the Read DMA, the following assignments illustrate
construction of a read descriptor:
a. RD_RC_LOW_SRC_ADDR = 0x0000 (The base address for the read descriptor table in
the Root Port
b. RD_RC_HIGH_SRC_ADDR = 0x0004
c. RD_CTLR_LOW_DEST_ADDR 0x0008
d. RD_CTLR_HIGH_DEST_ADDR = 0x000C
e. RD_DMA_LAST_PTR = 0x0010
Writing the RD_DMA_LAST_PTR register starts operation.
5. For the Write DMA, the source address is the Avalon-MM address that the Write DMA module
should read. The destination address is the Root Port memory space allocated in Step 3. Specify the
DMA length in dwords. Assuming a base address of 0x100, for the Write DMA, the following
assignments illustrate construction of a write descriptor:
a. RD_RC_LOW_SRC_ADDR = 0x0100 (The base address for the read descriptor table in
the Root Port
b. WD_RC_HIGH_SRC_ADDR = 0x0104
c. WD_CTLR_LOW_DEST_ADDR 0x0108
d. WD_CTLR_HIGH_DEST_ADDR = 0x010C
e. WD_DMA_LAST_PTR = 0x0110
Writing the WD_DMA_LAST_PTR register starts operation.
6. To improve throughput, the Read DMA module copies the descriptor table to the Avalon-MM
memory before beginning operation. Specify the memory address by writing to the EP Descriptor
Table Base (Low) and (High) registers.
7. An MSI interrupt is sent for each WD_DMA_LAST_PTR or RD_DMA_LAST_PTR that completes. These
completions result in updates to the done status bits. Host software can then read status bits to
determine which DMA operations are complete.
Note:
Out-of-order completions are supported for Read DMA requests. If the transfer size of the read
DMA is greater than the maximum read request size, the Read DMA creates multiple read
requests. For example, if Maximum Read Request Size is 512 bytes, the Read DMA breaks a
4 KByte read request into 8 requests with 8 different tags. The Read Completions can come back in
any order. The Read DMA Avalon-MM master port writes the Read Completions to the correct
locations, based on the tags.
UG-01154
2014.12.18
Software Program for Simultaneous Read and Write DMA
5-25
Registers
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- User Guide 1
- Features 3
- Interface 5
- Release Information 8
- Example Designs 9
- Debug Features 9
- IP Core Verification 9
- Related Information 10
- Altera Corporation 11
- Datasheet 11
- Send Feedback 11
- Parameter Value 17
- Directory Description 18
- Time TLP Type Payload 18
- TLP Header 18
- Creating a Quartus II Project 19
- Compiling the Design 20
- Parameter Settings 22
- Parameter Value Description 23
- Device Capabilities 28
- Error Reporting 28
- Link Capabilities 29
- MSI and MSI-X Capabilities 29
- Power Management 30
- PCIe Address Space Settings 31
- RX Master Module 36
- TX Slave Module 38
- Signal Name Directio 39
- Description 39
- Bits Name Description 41
- Clock Signals 45
- Signal Direction Description 46
- MSI Interrupts for Endpoints 51
- Serial Data Signals 53
- 9 Ch 18 Ch 54
- PIPE Interface Signals 64
- Test Signals 68
- Registers 70
- Altera-Defined VSEC Registers 77
- CvP Registers 78
- Bits Register Description 82
- Register Access Description 86
- Read DMA Example 91
- Byte Offset 95
- Register Dir Description 95
- Reset and Clocks 100
- Example Design 101
- Hard IP for PCI Express 101
- UG-01154 102
- 2014.12.18 102
- Clock Domains 104
- Data Rate Frequency 105
- Clock Summary 106
- Error Handling 107
- Physical Layer Errors 108
- Data Link Layer Errors 108
- Transaction Layer Errors 109
- Error Type Description 110
- Status Bit Conditions 112
- IP Core Architecture 114
- Hard IP for PCI Express 115
- Top-Level Interfaces 116
- Avalon-MM DMA Interface 116
- Clocks and Reset 116
- Transceiver Reconfiguration 116
- Interrupts 116
- Data Link Layer 117
- Physical Layer 119
- TX Packets 120
- Altera FPGA 122
- Qsys System 123
- Subscribe 125
- Address[31:2] 130
- Figure A-6: I/O Read Request 132
- Additional Information 136
- Date Version Changes Made 137
- How to Contact Altera 139
- Typographic Conventions 140
- Visual Cue Meaning 141
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