Altera V-Series Avalon-MM DMA Manual de usuario Pagina 137
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Valorado. / 5. Basado en revisión del cliente
Date Version Changes Made
2014.08.18 14.0 Arria 10
Made the following changes to the V-Series Avalon-MM DMA for
PCI Express IP core:
• Revised programming model for the Descriptor Controller.
• Added simulation log file, altpcie_monitor_a10_dlhip_tlp_file_log.log,
that is automatically generated in your simulation directory. To
simulate in the Quartus II 14.0 software release, you must
regenerate your IP core to create the supporting monitor file the
generates altpcie_monitor_a10_dlhip_tlp_file_log.log. Refer to
Understanding Simulation Dump File Generation for details.
• Added support for either 128- or 256-bit interface to the Applica‐
tion Layer.
• Added support for 64-bit addressing, making address translation
unnecessary.
• Removed Channel Placement for PCIe in Arria 10 Devices. Please
contact your Altera sales representative for PLL and channel
usage.
• Added support for optional bursting RX Master for BAR2.
• Revised Read DMA Example and Software Program for Simulta‐
neous Read and Write DMA to work with revised programming
model for the Descriptor Controller.
• Added the following optimizations for the Descriptor Controller:
• Optimized performance for smaller payloads such as 64-byte
Ethernet packets
• Reduced overhead for host updates
• Support for concurrent dynamic host updates and DMA
operation
• Support for choice to embed Descriptor Controller in the
Avalon-MM bridge or instantiate separately
• Added access to selected Configuration Space registers and link
status registers through the optional Control Register Access
(CRA) Avalon-MM slave port.
• Added simulation support for Phase 2 and Phase 3 equalization
when requested by third-party BFM for Gen3 variants.
• Added multiple MSI/MSI-X support.
B-2
Revision History for the Avalon-MM Interface with DMA
UG-01154
2014.12.18
Altera Corporation
Additional Information
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- User Guide 1
- Features 3
- Interface 5
- Release Information 8
- Example Designs 9
- Debug Features 9
- IP Core Verification 9
- Related Information 10
- Altera Corporation 11
- Datasheet 11
- Send Feedback 11
- Parameter Value 17
- Directory Description 18
- Time TLP Type Payload 18
- TLP Header 18
- Creating a Quartus II Project 19
- Compiling the Design 20
- Parameter Settings 22
- Parameter Value Description 23
- Device Capabilities 28
- Error Reporting 28
- Link Capabilities 29
- MSI and MSI-X Capabilities 29
- Power Management 30
- PCIe Address Space Settings 31
- RX Master Module 36
- TX Slave Module 38
- Signal Name Directio 39
- Description 39
- Bits Name Description 41
- Clock Signals 45
- Signal Direction Description 46
- MSI Interrupts for Endpoints 51
- Serial Data Signals 53
- 9 Ch 18 Ch 54
- PIPE Interface Signals 64
- Test Signals 68
- Registers 70
- Altera-Defined VSEC Registers 77
- CvP Registers 78
- Bits Register Description 82
- Register Access Description 86
- Read DMA Example 91
- Byte Offset 95
- Register Dir Description 95
- Reset and Clocks 100
- Example Design 101
- Hard IP for PCI Express 101
- UG-01154 102
- 2014.12.18 102
- Clock Domains 104
- Data Rate Frequency 105
- Clock Summary 106
- Error Handling 107
- Physical Layer Errors 108
- Data Link Layer Errors 108
- Transaction Layer Errors 109
- Error Type Description 110
- Status Bit Conditions 112
- IP Core Architecture 114
- Hard IP for PCI Express 115
- Top-Level Interfaces 116
- Avalon-MM DMA Interface 116
- Clocks and Reset 116
- Transceiver Reconfiguration 116
- Interrupts 116
- Data Link Layer 117
- Physical Layer 119
- TX Packets 120
- Altera FPGA 122
- Qsys System 123
- Subscribe 125
- Address[31:2] 130
- Figure A-6: I/O Read Request 132
- Additional Information 136
- Date Version Changes Made 137
- How to Contact Altera 139
- Typographic Conventions 140
- Visual Cue Meaning 141
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