Altera V-Series Avalon-MM DMA Manual de usuario Pagina 29
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Link Capabilities
Table 3-6: Link Capabilities
Parameter Value Description
Link port
number
0x01 Sets the read-only value of the port number field in the Link
Capabilities register.
Slot clock
configuration
On/Off When On, indicates that the Endpoint or Root Port uses the
same physical reference clock that the system provides on the
connector. When Off, the IP core uses an independent clock
regardless of the presence of a reference clock on the
connector.
MSI and MSI-X Capabilities
Table 3-7: MSI and MSI-X Capabilities
Parameter Value Description
MSI messages
requested
1, 2, 4, 8, 16 Specifies the number of messages the Application Layer can
request. Sets the value of the Multiple Message Capable
field of the Message Control register, 0x050[31:16].
MSI-X Capabilities
Implement MSI-X On/Off When On, enables the MSI-X functionality.
Bit Range
Table size [10:0] System software reads this field to determine the MSI-X Table
size <n>, which is encoded as <n–1>. For example, a returned
value of 2047 indicates a table size of 2048. This field is read-
only. Legal range is 0–2047 (2
11
).
Address offset: 0x068[26:16]
Table Offset [31:0] Points to the base of the MSI-X Table. The lower 3 bits of the
table BAR indicator (BIR) are set to zero by software to form a
32-bit qword-aligned offset. This field is read-only.
Table BAR
Indicator
[2:0] Specifies which one of a function’s BARs, located beginning at
0x10 in Configuration Space, is used to map the MSI-X table
into memory space. This field is read-only. Legal range is 0–5.
3-8
Link Capabilities
UG-01154
2014.12.18
Altera Corporation
Parameter Settings
Send Feedback
- User Guide 1
- Features 3
- Interface 5
- Release Information 8
- Example Designs 9
- Debug Features 9
- IP Core Verification 9
- Related Information 10
- Altera Corporation 11
- Datasheet 11
- Send Feedback 11
- Parameter Value 17
- Directory Description 18
- Time TLP Type Payload 18
- TLP Header 18
- Creating a Quartus II Project 19
- Compiling the Design 20
- Parameter Settings 22
- Parameter Value Description 23
- Device Capabilities 28
- Error Reporting 28
- Link Capabilities 29
- MSI and MSI-X Capabilities 29
- Power Management 30
- PCIe Address Space Settings 31
- RX Master Module 36
- TX Slave Module 38
- Signal Name Directio 39
- Description 39
- Bits Name Description 41
- Clock Signals 45
- Signal Direction Description 46
- MSI Interrupts for Endpoints 51
- Serial Data Signals 53
- 9 Ch 18 Ch 54
- PIPE Interface Signals 64
- Test Signals 68
- Registers 70
- Altera-Defined VSEC Registers 77
- CvP Registers 78
- Bits Register Description 82
- Register Access Description 86
- Read DMA Example 91
- Byte Offset 95
- Register Dir Description 95
- Reset and Clocks 100
- Example Design 101
- Hard IP for PCI Express 101
- UG-01154 102
- 2014.12.18 102
- Clock Domains 104
- Data Rate Frequency 105
- Clock Summary 106
- Error Handling 107
- Physical Layer Errors 108
- Data Link Layer Errors 108
- Transaction Layer Errors 109
- Error Type Description 110
- Status Bit Conditions 112
- IP Core Architecture 114
- Hard IP for PCI Express 115
- Top-Level Interfaces 116
- Avalon-MM DMA Interface 116
- Clocks and Reset 116
- Transceiver Reconfiguration 116
- Interrupts 116
- Data Link Layer 117
- Physical Layer 119
- TX Packets 120
- Altera FPGA 122
- Qsys System 123
- Subscribe 125
- Address[31:2] 130
- Figure A-6: I/O Read Request 132
- Additional Information 136
- Date Version Changes Made 137
- How to Contact Altera 139
- Typographic Conventions 140
- Visual Cue Meaning 141
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