Altera V-Series Avalon-MM DMA Manual de usuario Pagina 122
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Taking into account the overhead from TLP headers, this throughput is approximately 99% of the
maximum theoretical performance.
Using a 64-byte payload, the maximum theoretical throughput is far less due to the increased proportion
of the bandwidth that taken by the TLP headers. The DMA achieves the following throughput:
• 2.0 GBytes/sec back-to-back TX memory write completion
• 2.0 GBytes/sec back-to-back RX read completion throughput
• 2.0 GBytes/sec simultaneous reads and writes
Note: A 64-byte packet is worst-case packet size for Ethernet.
You can choose to include the DMA Descriptor Controller in the Avalon-MM bridge as shown in the
following example. Embedding the DMA Descriptor simplifies the design. Altera recommends that you
embed the DMA Descriptor Controller in the Avalon-MM bridge if you do not plan to modify it. Refer to
Getting Started with the V-Series Avalon-MM DMA for an example that includes the embedded DMA
Descriptor Controller.
Figure 8-4: Avalon-MM DMA Block Diagram with Embedded DMA Descriptor Controller
PCIe Avalon-MM Bridge
Hard IP for PCIe Using Avalon-MM Interface
Altera FPGA
Qsys System
with Internal Descriptor Controller
Memory
Read DMA
Write DMA
Hard IP
for PCIe
RX Master
TX Slave
DMA
Descriptor
Controller
Avalon-MM Burst
Master 256 Bits
Avalon-MM Burst
Master 256 Bits
Avalon-MM Master
Avalon-MM Slave Single DWORD
Avalon-ST Control/Status
Avalon-ST
256 Bits
FIFO
Internal Conduit
UG-01154
2014.12.18
V-Series Avalon-MM DMA for PCI Express
8-9
IP Core Architecture
Altera Corporation
Send Feedback
- User Guide 1
- Features 3
- Interface 5
- Release Information 8
- Example Designs 9
- Debug Features 9
- IP Core Verification 9
- Related Information 10
- Altera Corporation 11
- Datasheet 11
- Send Feedback 11
- Parameter Value 17
- Directory Description 18
- Time TLP Type Payload 18
- TLP Header 18
- Creating a Quartus II Project 19
- Compiling the Design 20
- Parameter Settings 22
- Parameter Value Description 23
- Device Capabilities 28
- Error Reporting 28
- Link Capabilities 29
- MSI and MSI-X Capabilities 29
- Power Management 30
- PCIe Address Space Settings 31
- RX Master Module 36
- TX Slave Module 38
- Signal Name Directio 39
- Description 39
- Bits Name Description 41
- Clock Signals 45
- Signal Direction Description 46
- MSI Interrupts for Endpoints 51
- Serial Data Signals 53
- 9 Ch 18 Ch 54
- PIPE Interface Signals 64
- Test Signals 68
- Registers 70
- Altera-Defined VSEC Registers 77
- CvP Registers 78
- Bits Register Description 82
- Register Access Description 86
- Read DMA Example 91
- Byte Offset 95
- Register Dir Description 95
- Reset and Clocks 100
- Example Design 101
- Hard IP for PCI Express 101
- UG-01154 102
- 2014.12.18 102
- Clock Domains 104
- Data Rate Frequency 105
- Clock Summary 106
- Error Handling 107
- Physical Layer Errors 108
- Data Link Layer Errors 108
- Transaction Layer Errors 109
- Error Type Description 110
- Status Bit Conditions 112
- IP Core Architecture 114
- Hard IP for PCI Express 115
- Top-Level Interfaces 116
- Avalon-MM DMA Interface 116
- Clocks and Reset 116
- Transceiver Reconfiguration 116
- Interrupts 116
- Data Link Layer 117
- Physical Layer 119
- TX Packets 120
- Altera FPGA 122
- Qsys System 123
- Subscribe 125
- Address[31:2] 130
- Figure A-6: I/O Read Request 132
- Additional Information 136
- Date Version Changes Made 137
- How to Contact Altera 139
- Typographic Conventions 140
- Visual Cue Meaning 141
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