Altera LVDS SERDES Transmitter / Receiver Manual de usuario Pagina 72
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Valorado. / 5. Basado en revisión del cliente
Date Version Changes
December 2008 v4.0 Updated for the Quartus II software 8.1:
• Removed figures.
• Added Stratix IV to Device Family Support.
• Updated Table 3, Table 4, Table 5, Table 6, Table 7, Table 8, Table
12, Table 13, Table 15,Table 3-1, Table 3-2, Table 3-3, Table 3-4,
and Table 3-6.
• Added Enable bitslip control, Enable independent bitslips controls
for each channel, and Register the bitslip control input using 'rx_
outclock' parameters and descriptions Table 11.
• Updated steps in Functional Results-Simulate the ALTLVDS
Receiver/Transmitter Design in the ModelSim-Altera Software,
Functional Results-Simulate the ALTLVDS Receiver/Transmitter
Design in the Quartus II Software, "Functional Results-Simulatethe
ALTLVDS Receiver/Transmitter Design in the ModelSim-Altera
Software".
• Added tx_syncclock and descriptions in Table 3-1.
• Added rx_data_align and rx_syncclock in Table 3-4.
• Updated descriptions in Table 3-6.
May 2008 v3.4 Small changes to Table 2-7 on page 2-27 and Table 2-9 on page 2-32.
November 2007 v3.3 Updated for the Quartus
®
II software v7.2, including:
• Added soft-CDR mode.
• Added description of new receiver output port rx_divfwdclk[].
• Added description of new receiver parameters enable_soft_cdr, is_
negative_ppm_drift,net_ppm_variation, enable_dpa_align_to_
rising_edge_only, dpa_initial_phase_ value, and enable_dpa_
initial_phase _selection.
• Updated two design examples.
• Added third design example using soft-CDR mode.
March 2007 v3.2 Updated for Quartus II software 7.0, including Cyclone
®
III informa‐
tion.
December 2006 v3.1 Updated Table 1-1 to include Stratix
®
III information.
November 2006 v3.0 Updated for the Quartus II software 6.1.
June 2006 v2.0 Updated for the Quartus II software 6.0.
August 2005 v1.1 Minor content changes.
December 2004 v1.0 Initial release.
72
Document Revision History
UG-MF9504
2014.12.15
Altera Corporation
LVDS SERDES Transmitter/Receiver IP Cores User Guide
Send Feedback
- Features 1
- Features Supported devices 2
- Related Information 2
- Clock Type J = Even J = Odd 3
- Using the Parameter Editor 5
- Upgrading IP Cores 8
- Parameter Settings 10
- Option Description 11
- ALTLVDS_RX Parameter Settings 16
- Parameter Type Description 26
- OUTCLOCK_DIVIDE_BY Value 32
- ALTLVDS_TX Ports 40
- UG-MF9504 41
- 2014.12.15 41
- ALTLVDS_RX Ports 42
- Functional Description 46
- DPA Mode 47
- Non-DPA Mode 47
- Soft-CDR Mode 47
- DPA PLL Calibration 49
- Initialization and Reset 51
- Resetting the DPA 52
- Aligning the Word Boundaries 53
- Dedicated SERDES 54
- SERDES in LEs 54
- Altera Corporation 56
- Send Feedback 56
- Port Name Constraint Type 60
- GUI Setting SDC command 60
- Compensation Report Panel 61
- FPGA Fabric 63
- Parameter/Clock Setting 64
- D1 D2 D3 D4 D5 D6 D7 D8 65
- Quartus II 66
- Design Flow 66
- Gate-Level Simulation 66
- RTL Simulation 66
- Document Revision History 67
- Date Version Changes 68
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