Altera LVDS SERDES Transmitter / Receiver Manual de usuario descargar pdf (Pagina 53)

The word aligner or the bit-slip circuit can be reset using the rx_cda_reset port. This circuit can be reset

anytime and is not dependent on the PLL or DPA circuit operation.

Aligning the Word Boundaries

To align the word boundaries, it is useful to have control characters in the data stream so that your logic

can have a known pattern to search for. You can compare the data received for each channel, compare to

the control character you are looking for, then pulse the rx_channel_data_align port as required until

you successfully receive the control character.

Note: Altera recommends setting the rx_cda_max[] port to the deserialization factor or higher, which

allows enough depth in the bit slip circuit to roll through an entire word if required.

If you do not have control characters in the received data, you need a deterministic relationship between

the reference clock and data to predict the word boundary using timing simulation or laboratory

measurements. The only way to ensure a deterministic relationship on the default word position in the

SERDES when the device powers up, or anytime the PLL is reset, is to have a reference clock equal to the

data rate divided by the deserialization factor. For example, if the data rate is 800 Mbps, and the deseriali‐

zation factor is 8, the PLL requires a 100-MHz reference clock. This is important because the PLL locks to

the rising edge of the reference clock. If you have one rising edge on the reference clock per serial word

received, the deserializer always starts at the same position. Using timing simulation, or lab measure‐

ments, monitor the parallel words received and determine how many pulses are required on the

rx_channel_data_align port to set your word boundaries. You can create a simple state machine to

apply the required number of pulses when you enter user mode, or anytime you reset the PLL and DPA

blocks.

Recommended Initialization and Reset Flow

Altera recommends that you follow these steps to initialize and reset the ALTLVDS IP cores:

1. During entry into user mode, or anytime in user mode operation when the interface requires a reset,

assert the pll_areset and rx_reset ports.

2. Deassert the pll_areset port and monitor the rx_locked port (rx_locked is the PLL lock indicator).

3. Deassert the rx_reset port after the rx_locked port becomes asserted and stable.

4. Apply the DPA training pattern and allow the DPA circuit to lock. (If a training pattern is not

available, any data with transitions is required to allow the DPA to lock.) Refer to the respective device

data sheet for DPA lock time specifications.

5. Wait for the rx_dpa_locked port to assert.

6. Beginning with Stratix III, HardCopy III, Arria II GX, and Arria II GZ devices, assert rx_fifo_reset

for at least one parallel clock cycle, and then de-assert rx_fifo_reset.

7. Assert the rx_cda_reset port for at least one parallel clock cycle, and then deassert the rx_cda_reset

port.

8. Begin word alignment by applying pulses as required to the rx_channel_data_align port.

9. When the word boundaries are established on each channel, the interface is ready for operation.

Source-Synchronous Timing Analysis and Timing Constraints

This section defines the source-synchronous differential data orientation timing parameters, the timing

budget definitions, and how to use these timing parameters to determine a design’s maximum perform‐

ance.

Different modes of LVDS receivers use different specifications in deciding the ability to sample the

received serial data correctly.

UG-MF9504

2014.12.15

Aligning the Word Boundaries

LVDS SERDES Transmitter/Receiver IP Cores User Guide

Altera Corporation

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