Altera LVDS SERDES Transmitter / Receiver Manual de usuario descargar pdf (Pagina 58)

To obtain the TCCS report (report_TCCS), follow these steps:

1. In the Quartus II software, under the Tools menu, click TimeQuest Timing Analyzer.

2. From the TimeQuest Timing Analyzer, under Reports, select Device Specific and click Report TCCS.

Setting Timing Constraints Using the TimeQuest Timing Analyzer GUI

Timing constraints for the LVDS receiver are needed only for the input clock ports and the synchronous

input ports. The synchronous output ports and the asynchronous input and output ports are set to false

path.

Constraining the Input Clock Signal

To constrain the input clock signal in the TimeQuest Timing Analyzer, follow these steps:

1. Run full compilation for the LVDS design. Ensure that the timing analysis tool is set to TimeQuest

Timing Analyzer.

2. After full compilation completes, on the Tools menu, select TimeQuest Timing Analyzer to launch

the TimeQuest analyzer window.

3. In the Tasks list, under Diagnostic, click Report Unconstrained Paths to view the list of

unconstrained paths and ports of the LVDS design.

4. In the Report list, under Unconstrained Paths, click Clock Status Summary to view the clock that

requires constraints. The default setting for all unconstrained clocks is 1 GHz. To constrain the clock

signal, right-click the clock name and select Edit Clock Constraint.

5. In the Create Clock dialog box, set the period and the clock rising and falling edge (duty cycle of the

clock) constraint. Refer to Table 12 for timing constraints options and descriptions.

6. Click Run.

Constraining the Synchronous Input Ports

Constrain the synchronous input signals for non-DPA mode SERDES to allow the TimeQuest Timing

Analyzer to consider your board channel-to-channel skew in the RSKM report. Without these constraints,

you need to subtract the board channel-to-channel skew from the RSKM value reported by the

TimeQuest Timing Analyzer.

To constrain the synchronous input signals in the TimeQuest Timing Analyzer, follow these steps:

1. Run full compilation for the LVDS design. Ensure that the timing analysis tool is set to TimeQuest

Timing Analyzer.

2. After full compilation completes, on the Tools menu, select TimeQuest Timing Analyzer to launch

the TimeQuest analyzer window.

3. In the Tasks list, under Diagnostic, double-click Report Unconstrained Paths to view the list of

unconstrained paths and ports of the LVDS design.

4. In the Report list, under Unconstrained Paths category, expand the Setup Analysis folder, and then

click Unconstrained Input Ports.

5. Set constraints for all the receiver synchronous input ports in the From list. To set input delay,

perform the following steps:

Setting Timing Constraints Using the TimeQuest Timing Analyzer GUI

UG-MF9504

2014.12.15

Altera Corporation

LVDS SERDES Transmitter/Receiver IP Cores User Guide

Send Feedback

1 2 ... 53 54 55 56 57 58 59 60 61 62 63 ... 71 72

Comentarios a estos manuales

Sin comentarios

Altera LVDS SERDES Transmitter / Receiver Manual de usuario Pagina 58

Comentarios a estos manuales

Relacionado con productos y manuales para Instrumentos de medición Altera LVDS SERDES Transmitter / Receiver