Altera LVDS SERDES Transmitter / Receiver Manual de usuario descargar pdf (Pagina 42)

Related Information

• Introduction to Altera IP Cores

• PLL Clock Signals for LVDS Interface in External PLL Mode on page 62

ALTLVDS_RX Ports

The following table lists the input and output ports for the ALTLVDS_RX IP core.

Note: n is the number of channels. m is the deserialization_factor × number_of_channels.

Table 11: ALTLVDS_RX Input and Output Ports

For Stratix IV, Arria II, and Cyclone IV devices, use the ALTPLL IP core. For Stratix V, Arria V, and Cyclone V

devices use the Altera PLL IP core.

Port Name Direction Width (Bit) Description

dpa_pll_recal Input 1 Enables dynamic recalibration without

resetting the DPA circuitry or the PLL. Only

available in DPA mode when PLL calibration

is enabled.

pll_areset Input 1 Asynchronously resets all counters to initial

values. The minimum pulse width require‐

ment for this signal is 10 ns.

pll_phasedone Input 1 Specifies whether dynamic phase reconfigura‐

tion is complete. Only available when using

an external PLL when PLL calibration is

enabled.

rx_cda_reset Input n

Asynchronous reset to the data realignment

circuitry. The minimum pulse width require‐

ment for this reset is one parallel clock cycle.

This signal resets the data realignment block.

This port is not available for Arria V and

Cyclone V devices. You can reset the CDA or

bitslip in Arria V and Cyclone V devices by

asserting the rx_channel_data_align signal

until the bitslip counter rolls over.

rx_channel_data_align Input n Controls byte alignment circuitry.

rx_coreclk Input n LVDS reference input clock. Replaces the

non-peripheral clock from the PLL. One clock

for each channel.

rx_data_align Input 1 Controls byte alignment circuitry. You can

This port is available when implement_in_

les parameter is set to ON and can be

implemented using flexible LVDS.

ALTLVDS_RX Ports

UG-MF9504

2014.12.15

Altera Corporation

LVDS SERDES Transmitter/Receiver IP Cores User Guide

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