Altera LVDS SERDES Transmitter / Receiver Manual de usuario descargar pdf (Pagina 52)

by-channel basis. If the PLL has not locked to a stable clock source, the DPA circuit might lock pre-

maturely to a non-ideal phase tap. Use the rx_reset port to keep the DPA in reset until the PLL lock

signal is asserted and stable.

In Stratix GX, Stratix II, Stratix II GX, HardCopy II, and Arria GX devices, when using the rx_reset port,

the ALTLVDS_RX parameter editor allows you to choose whether or not to automatically reset the bit

serial FIFO when the rx_dpa_locked signal asserts for the first time. This is a useful feature because it

keeps the synchronizer FIFO in reset until the DPA locks. To provide optimal timing between the DPA

domain, it is important to keep the FIFO in reset until the DPA locks.

With Stratix III, HardCopy III, Arria II GX, Arria II GZ devices and later generations of these devices, the

rx_dpa_lock signal asserts only after a specific number of transitions are detected in the parallel data

stream. You must not assert rx_fifo_reset port until the rx_dpa_lock signal asserts, otherwise, there

will be no data transitions in the parallel data, and the rx_dpa_lock signal will never assert.

Note:

Altera recommends asserting the rx_fifo_reset port after the rx_dpa_locked signal asserts, and

then deassert the rx_fifo_reset port to begin receiving data.

Each time the DPA shifts the phase taps during normal operation to track variations between the relation‐

ship of the reference clock source and the data, the timing margin for the data transfer between clock

domains is reduced.

For Stratix GX, Stratix II, Stratix II GX, HardCopy II, and Arria GX devices, when the ALTLVDS_RX IP

core deasserts the rx_dpa_locked port to indicate that the DPA has selected a new phase tap to capture

the data. You can choose the options in the ALTLVDS_RX parameter editor if you want the DPA lock

signal to deassert after one phase step, or after two phase steps in the same direction (check device family

availability for this option).

With Stratix III, HardCopy III, Arria II GX, Arria II GZ devices and later generations of these devices, the

ALTLVDS_RX asserts the rx_dpa_locked port upon initial DPA lock. This port remains asserted

throughout the operation until the ALTLVDS_RX IP core asserts the rx_reset or rx_dpa_lock_reset

ports. The rx_dpa_locked port does not indicate if the DPA has selected a new phase.

Note:

Altera recommends using the data checkers to ensure data accuracy.

Resetting the DPA

When the data becomes corrupted, you must reset the DPA circuitry using the rx_reset port and

rx_fifo_reset port.

Assert the rx_reset port to reset the entire DPA block. This requires the DPA to be trained before it is

ready for data capture.

Note:

Altera recommends using the option to automatically reset the bit serial FIFO when the

rx_dpa_locked signal rises for the first time, if available for your device family; otherwise, toggle

the rx_fifo_reset port after rx_dpa_locked is asserted. This option ensures the synchronization

FIFO is set with the optimal timing to transfer data between the DPA and high-speed LVDS clock

domains.

Assert the rx_fifo_reset port to reset only the synchronization FIFO. This allows you to continue

system operation without having to re-train the DPA. Using this port can fix data corruption because it

resets the FIFO; however, it does not reset the DPA circuit. In Stratix GX, Stratix II, Stratix II GX,

HardCopy II, and Arria GX devices, the rx_dpa_locked port remains in its previous state; if it was

deasserted, it remains deasserted and you are not be able to use it to know when the DPA is using the ideal

phase tap for data capture.

When the DPA is locked, the ALTLVDS block is ready to capture data. The DPA finds the optimal sample

location to capture each bit. The next step is to set up the word boundary using custom logic to control

the rx_channel_data_align port on a channel-by-channel basis.

Resetting the DPA

UG-MF9504

2014.12.15

Altera Corporation

LVDS SERDES Transmitter/Receiver IP Cores User Guide

Send Feedback

1 2 ... 47 48 49 50 51 52 53 54 55 56 57 ... 71 72

Comentarios a estos manuales

Sin comentarios

Altera LVDS SERDES Transmitter / Receiver Manual de usuario Pagina 52

Comentarios a estos manuales

Relacionado con productos y manuales para Instrumentos de medición Altera LVDS SERDES Transmitter / Receiver