Altera LVDS SERDES Transmitter / Receiver Manual de usuario descargar pdf (Pagina 49)

Figure 8: ALTLVDS_RX Block in No Output Register Mode

DPA

ALTLVDS_RX Core

ALTLVDS_RX

fast registers

ALTLVDS_RX

slow registers

divfwdclk

rx_out[]

rx_divfwdclk

DPA PLL Calibration

The following sections describe DPA PLL calibration and its effects in Stratix III, Stratix IV,

Stratix IV Engineering Sample (ES), and Arria II devices.

• DPA PLL Calibration in Stratix IV ES Devices on page 49

• DPA PLL Calibration in Arria II and Stratix IV Devices and Later on page 50

• Effects of DPA PLL Calibration on page 51

Related Information

High-Speed Differential I/O Interfaces and DPA in Arria V Devices, Volume 1: Device Interfaces and

Intergration, Arria V Device Handbook

DPA PLL Calibration in Stratix IV ES Devices

Applications using a fixed, cyclical training pattern with sparse data transitions can cause the PLL phase

to remain unchanged, which results in DPA misalignment. When DPA misaligns the DPA circuitry

remains at the initial configured phase or takes a significantly longer time to lock onto the optimum

phase. A non-ideal phase might result in data bit errors, even after the DPA lock signal goes high.

Resetting the DPA circuit may not solve the problem.

The following figure shows that the DPA takes longer time to lock onto the optimum phase even after the

rx_reset and rx_dpa_locked signals are asserted, resulting in data errors.

UG-MF9504

2014.12.15

DPA PLL Calibration

LVDS SERDES Transmitter/Receiver IP Cores User Guide

Altera Corporation

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Altera LVDS SERDES Transmitter / Receiver Manual de usuario Pagina 49