Altera JESD204B IP Manual de usuario Pagina 96
- Pagina / 158
- Tabla de contenidos
- MARCADORES
Valorado. / 5. Basado en revisión del cliente
Signal Clock Domain Direction Description
csr_l[4:0]
(31)
mgmt_clk
Input
Indicates the number of active lanes for the link.
This 5-bit bus represents the L value in zero-
based binary format. For example, if L = 1, the
csr_l[4:0] = "00000". This design example
supports the following values:
• 00000
• 00001
• 00011
• 00111
Any programmed value beyond the supported
range may result in undeterminable behavior in
the transport layer. You must ensure that the
csr_l[4:0] value always matches the system
parameter L value when it is in static configura‐
tion.
Runtime reconfiguration supports L fallback. For
static configuration, set the maximum L and
reconfigure csr_l[] to a smaller value during
runtime. This transport layer only supports
higher index channels to be powered down. To
interleave the de-commision channels, you need
to modify the interface connection from the DLL
to transport layer.
Connect this signal to the TX DLL csr_l[]
output pin.
csr_f[7:0]
(31)
mgmt_clk
Input
Indicates the number of octets per frame. This 8-
bit bus represents the F value in zero-based
binary format. For example, if F = 2, the csr_
f[7:0] = "00000001". This design example
supports the following values:
• 00000000
• 00000001
• 00000011
• 00000111
Any programmed value beyond the supported
range may result in undeterminable behavior in
the transport layer. Ensure that the csr_f[7:0]
value always matches the system parameter F
value when it is in static configuration. Connect
this signal to the TX DLL csr_f[] output pin.
(31)
This signal should be static and valid before the deassertion of the link_rst_n and frame_rst_n signals.
UG-01142
2015.05.04
TX Path
5-15
JESD204B IP Core Design Guidelines
Altera Corporation
Send Feedback
- JESD204B IP Core User Guide 1
- Contents 2
- Item Description 4
- Datapath Modes 8
- IP Core Variation 8
- Run-Time Configuration 9
- Channel Bonding 10
- About the JESD204B IP Core 13
- Getting Started 15
- Upgrading IP Cores 16
- IP Core Status Description 17
- Design Walkthrough 20
- Programming an FPGA Device 25
- Pin Assignments 26
- JESD204B IP Core Parameters 30
- Parameter Value Description 31
- JESD204B IP Core Testbench 35
- Configuration Preset Value 36
- Testbench Simulation Flow 37
- Subscribe 38
- Frame Clock 39
- Transmitter 41
- TX Data Link Layer 42
- Configura‐ 43
- Description 43
- MSB 6 5 4 3 2 1 LSB 43
- User Data Phase 44
- Receiver 45
- RX Data Link Layer 46
- Frame Alignment 47
- Lane Alignment 47
- ILAS Data 48
- Initial Lane Synchronization 48
- RX PHY Layer 49
- Operation 50
- Scrambler/Descrambler 51
- SYNC_N Signal 51
- Link Reinitialization 53
- Link Startup Sequence 54
- Device Clock 57
- Link Clock 58
- Local Multi-Frame Clock 59
- Clock Correlation 60
- Reset Scheme 61
- Reset Sequence 62
- Registers 80
- Access Type Definition 81
- Design Example Components 84
- PLL Reconfiguration 85
- Operation Avalon-MM 86
- Interface Signal 86
- Byte Address 86
- Offset (6bits) 86
- Bit Value 86
- Transceiver Reset Controller 87
- Pattern Generator 87
- Pattern Checker 88
- Transport Layer 89
- F Parameter f 90
- (txframe_clk frequency) f 90
- (rxframe_clk frequency) 90
- TX Path Data Remapping 100
- Altera Corporation 100
- Send Feedback 100
- UG-01142 104
- 2015.05.04 104
- F FRAMECLK_DIV TX Latency 105
- Parameter Description Value 106
- Related Information 113
- RX Path Data Remapping 114
- Serial Port Interface (SPI) 117
- Control Unit 118
- Memory Block (ROM) 119
- Finite State Machine (FSM) 120
- System Parameters 121
- Run-Time Reconfiguration 124
- System Interface Signals 125
- Signal Clock 128
- Direction Description 128
- PHY (Stratix V and Arria V) 133
- Implementation Guidelines 139
- Programmable RBD Offset 140
- Programmable LMFC Offset 143
- K K K K K RK K K K K 146
- D D D DK D D 146
- DK D DK K K 146
- Clocking Scheme 148
- JESD204B Parameters 148
- SPI Programming 149
- Additional Information 155
- Date Version Changes 156
- How to Contact Altera 157
- Contact Method Address 158
Relacionado con productos y manuales para Instrumentos de medición Altera JESD204B IP
Instrumentos de medición Altera Nios II Embedded Evaluation Kit Cyclone III Editio Manual de usuario
(3 paginas)
(3 paginas)
Instrumentos de medición Altera Nios II Embedded Evaluation Kit Cyclone III Editio Manual de usuario
(80 paginas)
(80 paginas)
Instrumentos de medición Altera Phase-Locked Loop Reconfiguration IP Core Manual de usuario
(51 paginas)
(51 paginas)
Instrumentos de medición Altera Serial Digital Interface (SDI) MegaCore Function Manual de usuario
(140 paginas)
(140 paginas)
Instrumentos de medición Altera 100G Development Kit, Stratix V GX Edition Manual de usuario
(44 paginas)
(44 paginas)
Instrumentos de medición Altera Stratix V Avalon-MM Interface for PCIe Solutions Manual de usuario
(184 paginas)
(184 paginas)
Instrumentos de medición Altera 10-Gbps Ethernet MAC MegaCore Function Manual de usuario
(175 paginas)
(175 paginas)
© 2020, manymanuals.es. Todos los derechos reservados | 0.051 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Comentarios a estos manuales